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34df79fc9d
({extract,store}_{signed_integer,unsigned_integer,address}): New routines to replace SWAP_TARGET_AND_HOST. All over: All uses of SWAP_TARGET_AND_HOST on integers replaced.
183 lines
4.5 KiB
C
183 lines
4.5 KiB
C
/* i80960 instruction disassembler for GDB.
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Copyright 1990, 1991, 1992 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "dis-asm.h"
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/* Print the instruction at address MEMADDR in debugged memory,
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on STREAM. Returns length of the instruction, in bytes. */
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr;
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FILE *stream;
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{
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disassemble_info info;
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GDB_INIT_DISASSEMBLE_INFO(info, stream);
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return print_insn_i960 (memaddr, &info);
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}
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/****************************************/
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/* MEM format */
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/****************************************/
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struct tabent {
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char *name;
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char numops;
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};
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static int /* returns instruction length: 4 or 8 */
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mem( memaddr, word1, word2, noprint )
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unsigned long memaddr;
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unsigned long word1, word2;
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int noprint; /* If TRUE, return instruction length, but
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don't output any text. */
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{
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int i, j;
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int len;
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int mode;
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int offset;
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const char *reg1, *reg2, *reg3;
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/* This lookup table is too sparse to make it worth typing in, but not
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* so large as to make a sparse array necessary. We allocate the
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* table at runtime, initialize all entries to empty, and copy the
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* real ones in from an initialization table.
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*
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* NOTE: In this table, the meaning of 'numops' is:
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* 1: single operand
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* 2: 2 operands, load instruction
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* -2: 2 operands, store instruction
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*/
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static struct tabent *mem_tab = NULL;
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/* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
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#define MEM_MIN 0x80
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#define MEM_MAX 0xcf
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#define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
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static struct { int opcode; char *name; char numops; } mem_init[] = {
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0x80, "ldob", 2,
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0x82, "stob", -2,
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0x84, "bx", 1,
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0x85, "balx", 2,
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0x86, "callx", 1,
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0x88, "ldos", 2,
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0x8a, "stos", -2,
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0x8c, "lda", 2,
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0x90, "ld", 2,
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0x92, "st", -2,
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0x98, "ldl", 2,
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0x9a, "stl", -2,
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0xa0, "ldt", 2,
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0xa2, "stt", -2,
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0xb0, "ldq", 2,
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0xb2, "stq", -2,
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0xc0, "ldib", 2,
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0xc2, "stib", -2,
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0xc8, "ldis", 2,
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0xca, "stis", -2,
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0, NULL, 0
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};
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if ( mem_tab == NULL ){
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mem_tab = (struct tabent *) xmalloc( MEM_SIZ );
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bzero( mem_tab, MEM_SIZ );
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for ( i = 0; mem_init[i].opcode != 0; i++ ){
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j = mem_init[i].opcode - MEM_MIN;
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mem_tab[j].name = mem_init[i].name;
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mem_tab[j].numops = mem_init[i].numops;
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}
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}
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i = ((word1 >> 24) & 0xff) - MEM_MIN;
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mode = (word1 >> 10) & 0xf;
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if ( (mem_tab[i].name != NULL) /* Valid instruction */
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&& ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */
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len = 8;
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} else {
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len = 4;
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}
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if ( noprint ){
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return len;
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}
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abort ();
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}
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/* Read the i960 instruction at 'memaddr' and return the address of
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the next instruction after that, or 0 if 'memaddr' is not the
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address of a valid instruction. The first word of the instruction
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is stored at 'pword1', and the second word, if any, is stored at
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'pword2'. */
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CORE_ADDR
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next_insn (memaddr, pword1, pword2)
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unsigned long *pword1, *pword2;
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CORE_ADDR memaddr;
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{
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int len;
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char buf[8];
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/* Read the two (potential) words of the instruction at once,
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to eliminate the overhead of two calls to read_memory ().
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FIXME: Loses if the first one is readable but the second is not
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(e.g. last word of the segment). */
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read_memory (memaddr, buf, 8);
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*pword1 = extract_unsigned_integer (buf, 4);
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*pword2 = extract_unsigned_integer (buf + 4, 4);
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/* Divide instruction set into classes based on high 4 bits of opcode*/
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switch ((*pword1 >> 28) & 0xf)
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{
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case 0x0:
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case 0x1: /* ctrl */
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case 0x2:
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case 0x3: /* cobr */
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case 0x5:
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case 0x6:
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case 0x7: /* reg */
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len = 4;
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break;
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case 0x8:
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case 0x9:
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case 0xa:
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case 0xb:
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case 0xc:
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len = mem (memaddr, *pword1, *pword2, 1);
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break;
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default: /* invalid instruction */
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len = 0;
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break;
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}
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if (len)
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return memaddr + len;
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else
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return 0;
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}
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