mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
/* RISC-V simulator.
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Copyright (C) 2005-2024 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_MAIN_H
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#define RISCV_MAIN_H
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struct riscv_sim_cpu {
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union {
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unsigned_word regs[32];
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struct {
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/* These are the ABI names. */
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unsigned_word zero, ra, sp, gp, tp;
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unsigned_word t0, t1, t2;
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unsigned_word s0, s1;
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unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
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unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
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unsigned_word t3, t4, t5, t6;
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};
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};
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union {
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unsigned_word fpregs[32];
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struct {
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/* These are the ABI names. */
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unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
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unsigned_word fs0, fs1;
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unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
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unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
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unsigned_word ft8, ft9, ft10, ft11;
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};
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};
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sim_cia pc;
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struct {
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#define DECLARE_CSR(name, ...) unsigned_word name;
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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} csr;
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};
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#define RISCV_SIM_CPU(cpu) ((struct riscv_sim_cpu *) CPU_ARCH_DATA (cpu))
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struct atomic_mem_reserved_list;
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struct atomic_mem_reserved_list {
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struct atomic_mem_reserved_list *next;
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address_word addr;
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};
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struct riscv_sim_state {
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struct atomic_mem_reserved_list *amo_reserved_list;
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};
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#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
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extern void step_once (SIM_CPU *);
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extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
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extern void initialize_env (SIM_DESC, const char * const *argv,
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const char * const *env);
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#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
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#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
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#endif
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