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1d506c26d9
This commit is the result of the following actions: - Running gdb/copyright.py to update all of the copyright headers to include 2024, - Manually updating a few files the copyright.py script told me to update, these files had copyright headers embedded within the file, - Regenerating gdbsupport/Makefile.in to refresh it's copyright date, - Using grep to find other files that still mentioned 2023. If these files were updated last year from 2022 to 2023 then I've updated them this year to 2024. I'm sure I've probably missed some dates. Feel free to fix them up as you spot them.
178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
/* RISC-V simulator.
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Copyright (C) 2005-2024 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "bfd.h"
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#include "sim/callback.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "target-newlib-syscall.h"
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#include "riscv-sim.h"
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void
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sim_engine_run (SIM_DESC sd,
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int next_cpu_nr, /* ignore */
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int nr_cpus, /* ignore */
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int siggnal) /* ignore */
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{
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SIM_CPU *cpu;
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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cpu = STATE_CPU (sd, 0);
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while (1)
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{
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step_once (cpu);
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if (sim_events_tick (sd))
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sim_events_process (sd);
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}
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}
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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extern const SIM_MACH * const riscv_sim_machs[];
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *callback,
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struct bfd *abfd, char * const *argv)
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{
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char c;
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int i;
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SIM_DESC sd = sim_state_alloc_extra (kind, callback,
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sizeof (struct riscv_sim_state));
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/* Set default options before parsing user options. */
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STATE_MACHS (sd) = riscv_sim_machs;
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STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G";
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current_target_byte_order = BFD_ENDIAN_LITTLE;
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callback->syscall_map = cb_riscv_syscall_map;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct riscv_sim_cpu))
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!= SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* XXX: Default to the Virtual environment. */
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if (STATE_ENVIRONMENT (sd) == ALL_ENVIRONMENT)
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STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
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/* The parser will print an error message for us, so we silently return. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Check for/establish the a reference program image. */
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if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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initialize_cpu (sd, cpu, i);
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}
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/* Allocate external memory if none specified by user.
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Use address 4 here in case the user wanted address 0 unmapped. */
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if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
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sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEM_SIZE);
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return sd;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
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char * const *argv, char * const *env)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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host_callback *cb = STATE_CALLBACK (sd);
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bfd_vma addr;
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/* Set the PC. */
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if (abfd != NULL)
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addr = bfd_get_start_address (abfd);
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else
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addr = 0;
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sim_pc_set (cpu, addr);
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/* Standalone mode (i.e. `run`) will take care of the argv for us in
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sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
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with `gdb`), we need to handle it because the user can change the
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argv on the fly via gdb's 'run'. */
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if (STATE_PROG_ARGV (sd) != argv)
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{
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freeargv (STATE_PROG_ARGV (sd));
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STATE_PROG_ARGV (sd) = dupargv (argv);
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}
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if (STATE_PROG_ENVP (sd) != env)
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{
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freeargv (STATE_PROG_ENVP (sd));
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STATE_PROG_ENVP (sd) = dupargv (env);
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}
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cb->argv = STATE_PROG_ARGV (sd);
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cb->envp = STATE_PROG_ENVP (sd);
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initialize_env (sd, (void *)argv, (void *)env);
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return SIM_RC_OK;
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}
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