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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
138 lines
2.5 KiB
Plaintext
138 lines
2.5 KiB
Plaintext
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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start
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.global walignr
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walignr:
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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# Test 0 byte align
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r6, 3
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcr wcgr0, r6
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walignr0 wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrc r6, wcgr0
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0xbcdef012
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test_h_gr r5, 0x1111119a
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test_h_gr r6, 3
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# Test 1 byte align
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r6, 4
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcr wcgr1, r6
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walignr1 wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrc r6, wcgr1
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0x9abcdef0
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test_h_gr r5, 0x11111111
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test_h_gr r6, 4
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# Test 2 byte align
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r6, 2
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcr wcgr2, r6
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walignr2 wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrc r6, wcgr2
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0xdef01234
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test_h_gr r5, 0x11119abc
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test_h_gr r6, 2
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# Test 3 byte align
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r6, 5
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcr wcgr3, r6
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walignr3 wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrc r6, wcgr3
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0x119abcde
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test_h_gr r5, 0x00111111
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test_h_gr r6, 5
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pass
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