mirror of
https://sourceware.org/git/binutils-gdb.git
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279 lines
8.2 KiB
C
279 lines
8.2 KiB
C
/*
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* Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not
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* include this directly, but pull in x86-cpuid.h and use that func.
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*/
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/*
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* Copyright (C) 2007-2015 Free Software Foundation, Inc.
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*
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* This file is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 3, or (at your option) any
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* later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Under Section 7 of GPL version 3, you are granted additional
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* permissions described in the GCC Runtime Library Exception, version
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* 3.1, as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License and
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* a copy of the GCC Runtime Library Exception along with this program;
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* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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/* %ecx */
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#define bit_SSE3 (1 << 0)
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#define bit_PCLMUL (1 << 1)
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#define bit_LZCNT (1 << 5)
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#define bit_SSSE3 (1 << 9)
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#define bit_FMA (1 << 12)
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#define bit_CMPXCHG16B (1 << 13)
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#define bit_SSE4_1 (1 << 19)
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#define bit_SSE4_2 (1 << 20)
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#define bit_MOVBE (1 << 22)
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#define bit_POPCNT (1 << 23)
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#define bit_AES (1 << 25)
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#define bit_XSAVE (1 << 26)
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#define bit_OSXSAVE (1 << 27)
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#define bit_AVX (1 << 28)
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#define bit_F16C (1 << 29)
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#define bit_RDRND (1 << 30)
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/* %edx */
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#define bit_CMPXCHG8B (1 << 8)
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#define bit_CMOV (1 << 15)
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#define bit_MMX (1 << 23)
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#define bit_FXSAVE (1 << 24)
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#define bit_SSE (1 << 25)
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#define bit_SSE2 (1 << 26)
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/* Extended Features */
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/* %ecx */
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#define bit_LAHF_LM (1 << 0)
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#define bit_ABM (1 << 5)
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#define bit_SSE4a (1 << 6)
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#define bit_PRFCHW (1 << 8)
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#define bit_XOP (1 << 11)
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#define bit_LWP (1 << 15)
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#define bit_FMA4 (1 << 16)
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#define bit_TBM (1 << 21)
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/* %edx */
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#define bit_MMXEXT (1 << 22)
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#define bit_LM (1 << 29)
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#define bit_3DNOWP (1 << 30)
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#define bit_3DNOW (1 << 31)
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/* Extended Features (%eax == 7) */
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#define bit_FSGSBASE (1 << 0)
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#define bit_BMI (1 << 3)
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#define bit_HLE (1 << 4)
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#define bit_AVX2 (1 << 5)
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#define bit_BMI2 (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_AVX512F (1 << 16)
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#define bit_MPX (1 << 14)
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#define bit_RDSEED (1 << 18)
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#define bit_ADX (1 << 19)
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#define bit_AVX512PF (1 << 26)
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#define bit_AVX512ER (1 << 27)
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#define bit_AVX512CD (1 << 28)
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#define bit_SHA (1 << 29)
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/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
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#define bit_XSAVEOPT (1 << 0)
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/* Signatures for different CPU implementations as returned in uses
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of cpuid with level 0. */
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#define signature_AMD_ebx 0x68747541
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#define signature_AMD_ecx 0x444d4163
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#define signature_AMD_edx 0x69746e65
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#define signature_CENTAUR_ebx 0x746e6543
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#define signature_CENTAUR_ecx 0x736c7561
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#define signature_CENTAUR_edx 0x48727561
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#define signature_CYRIX_ebx 0x69727943
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#define signature_CYRIX_ecx 0x64616574
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#define signature_CYRIX_edx 0x736e4978
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#define signature_INTEL_ebx 0x756e6547
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#define signature_INTEL_ecx 0x6c65746e
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#define signature_INTEL_edx 0x49656e69
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#define signature_TM1_ebx 0x6e617254
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#define signature_TM1_ecx 0x55504361
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#define signature_TM1_edx 0x74656d73
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#define signature_TM2_ebx 0x756e6547
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#define signature_TM2_ecx 0x3638784d
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#define signature_TM2_edx 0x54656e69
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#define signature_NSC_ebx 0x646f6547
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#define signature_NSC_ecx 0x43534e20
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#define signature_NSC_edx 0x79622065
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#define signature_NEXGEN_ebx 0x4778654e
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#define signature_NEXGEN_ecx 0x6e657669
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#define signature_NEXGEN_edx 0x72446e65
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#define signature_RISE_ebx 0x65736952
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#define signature_RISE_ecx 0x65736952
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#define signature_RISE_edx 0x65736952
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#define signature_SIS_ebx 0x20536953
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#define signature_SIS_ecx 0x20536953
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#define signature_SIS_edx 0x20536953
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#define signature_UMC_ebx 0x20434d55
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#define signature_UMC_ecx 0x20434d55
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#define signature_UMC_edx 0x20434d55
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#define signature_VIA_ebx 0x20414956
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#define signature_VIA_ecx 0x20414956
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#define signature_VIA_edx 0x20414956
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#define signature_VORTEX_ebx 0x74726f56
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#define signature_VORTEX_ecx 0x436f5320
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#define signature_VORTEX_edx 0x36387865
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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#if __GNUC__ >= 3
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#else
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/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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nor alternatives in i386 code. */
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %k1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %k1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
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/* %rbx may be the PIC register. */
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
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"cpuid\n\t" \
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"xchg{q}\t{%%}rbx, %q1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
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"cpuid\n\t" \
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"xchg{q}\t{%%}rbx, %q1\n\t" \
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: "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#else
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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/* Return highest supported input value for cpuid instruction. ext can
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be either 0x0 or 0x8000000 to return highest supported value for
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basic or extended cpuid information. Function returns 0 if cpuid
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is not supported or whatever cpuid returns in eax register. If sig
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pointer is non-null, then first four bytes of the signature
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(as found in ebx register) are returned in location pointed by sig. */
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static __inline unsigned int
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__get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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{
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unsigned int __eax, __ebx, __ecx, __edx;
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#ifndef __x86_64__
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/* See if we can use cpuid. On AMD64 we always can. */
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#if __GNUC__ >= 3
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__asm__ ("pushf{l|d}\n\t"
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"pushf{l|d}\n\t"
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"pop{l}\t%0\n\t"
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"mov{l}\t{%0, %1|%1, %0}\n\t"
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"xor{l}\t{%2, %0|%0, %2}\n\t"
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"push{l}\t%0\n\t"
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"popf{l|d}\n\t"
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"pushf{l|d}\n\t"
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"pop{l}\t%0\n\t"
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"popf{l|d}\n\t"
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: "=&r" (__eax), "=&r" (__ebx)
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: "i" (0x00200000));
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#else
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/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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nor alternatives in i386 code. */
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__asm__ ("pushfl\n\t"
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"pushfl\n\t"
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"popl\t%0\n\t"
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"movl\t%0, %1\n\t"
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"xorl\t%2, %0\n\t"
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"pushl\t%0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl\t%0\n\t"
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"popfl\n\t"
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: "=&r" (__eax), "=&r" (__ebx)
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: "i" (0x00200000));
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#endif
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if (!((__eax ^ __ebx) & 0x00200000))
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return 0;
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#endif
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/* Host supports cpuid. Return highest supported cpuid input value. */
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__cpuid (__ext, __eax, __ebx, __ecx, __edx);
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if (__sig)
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*__sig = __ebx;
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return __eax;
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}
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/* Return cpuid data for requested cpuid level, as found in returned
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eax, ebx, ecx and edx registers. The function checks if cpuid is
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supported and returns 1 for valid cpuid information or 0 for
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unsupported cpuid level. All pointers are required to be non-null. */
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static __inline int
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__get_cpuid (unsigned int __level,
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unsigned int *__eax, unsigned int *__ebx,
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unsigned int *__ecx, unsigned int *__edx)
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{
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unsigned int __ext = __level & 0x80000000;
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if (__get_cpuid_max (__ext, 0) < __level)
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return 0;
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__cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
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return 1;
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}
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