Denis Chertykov 59f48f5a45 Update PC when simulate break instruction. ... PR target/ 19401 * avr/interp.c (step_once): Pass break instruction address to sim_engine_halt function which writes that to PC. Remove code that follows that function call as it is unreachable.		2016-07-19 09:47:23 +03:00
..
aarch64	Add support for simulating big-endian AArch64 binaries.	2016-06-30 09:10:41 +01:00
arm	Small improvements to the ARM simulator to cope with illegal binaries.	2016-07-14 10:38:07 +01:00
avr	Update PC when simulate break instruction.	2016-07-19 09:47:23 +03:00
bfin
common
cr16
cris
d10v
erc32
frv
ft32
h8300
igen
iq2000
lm32
m32c
m32r
m68hc11
mcore
microblaze
mips
mn10300
moxie
msp430
ppc
rl78
rx	Fix a typo in the check for SNANs in the RX simulator.	2016-04-27 12:37:11 +01:00
sh	Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.	2016-04-10 11:02:47 +09:00
sh64
testsuite
v850
.gitignore
ChangeLog	Update PC when simulate break instruction.	2016-07-19 09:47:23 +03:00
configure
configure.ac
configure.tgt
MAINTAINERS
Makefile.in
README-HACKING