binutils-gdb/sim/riscv
Mike Frysinger 883be19774 sim: cpu: change default init to handle all cpus
All the runtimes were only initializing a single CPU.  When SMP is
enabled, things quickly crash as none of the other CPU structs are
setup.  Change the default from 0 to the compile time value.
2022-12-25 02:10:46 -05:00
..
acinclude.m4 sim: riscv: add missing AC_MSG_RESULT call 2022-11-07 23:44:36 +07:00
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
interp.c sim: cpu: change default init to handle all cpus 2022-12-25 02:10:46 -05:00
local.mk sim: run: move linking into top-level 2022-11-05 20:00:56 +07:00
machs.c sim: riscv: move arch-specific settings to internal header 2022-12-23 08:32:58 -05:00
machs.h Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00
Makefile.in sim: riscv: drop subdir configure logic 2022-11-07 23:24:46 +07:00
model_list.def
riscv-sim.h sim: riscv: move arch-specific settings to internal header 2022-12-23 08:32:58 -05:00
sim-main.c sim: riscv: move arch-specific settings to internal header 2022-12-23 08:32:58 -05:00
sim-main.h sim: riscv: move arch-specific settings to internal header 2022-12-23 08:32:58 -05:00