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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
515 lines
15 KiB
C
515 lines
15 KiB
C
/* Instruction printing code for the DLX Microprocessor
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Copyright (C) 2002-2024 Free Software Foundation, Inc.
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Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "disassemble.h"
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#include "opcode/dlx.h"
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#define R_ERROR 0x1
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#define R_TYPE 0x2
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#define ILD_TYPE 0x3
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#define IST_TYPE 0x4
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#define IAL_TYPE 0x5
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#define IBR_TYPE 0x6
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#define IJ_TYPE 0x7
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#define IJR_TYPE 0x8
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#define NIL 0x9
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#define OPC(x) ((x >> 26) & 0x3F)
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#define FUNC(x) (x & 0x7FF)
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unsigned char opc, rs1, rs2, rd;
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unsigned long imm26, imm16, func, current_insn_addr;
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/* Print one instruction from MEMADDR on INFO->STREAM.
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Return the size of the instruction (always 4 on dlx). */
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static unsigned char
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dlx_get_opcode (unsigned long opcode)
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{
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return (unsigned char) ((opcode >> 26) & 0x3F);
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}
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static unsigned char
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dlx_get_rs1 (unsigned long opcode)
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{
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return (unsigned char) ((opcode >> 21) & 0x1F);
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}
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static unsigned char
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dlx_get_rs2 (unsigned long opcode)
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{
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return (unsigned char) ((opcode >> 16) & 0x1F);
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}
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static unsigned char
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dlx_get_rdR (unsigned long opcode)
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{
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return (unsigned char) ((opcode >> 11) & 0x1F);
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}
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static unsigned long
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dlx_get_func (unsigned long opcode)
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{
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return (unsigned char) (opcode & 0x7FF);
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}
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static unsigned long
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dlx_get_imm16 (unsigned long opcode)
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{
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return (unsigned long) (opcode & 0xFFFF);
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}
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static unsigned long
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dlx_get_imm26 (unsigned long opcode)
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{
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return (unsigned long) (opcode & 0x03FFFFFF);
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}
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/* Fill the opcode to the max length. */
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static void
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operand_deliminator (struct disassemble_info *info, char *ptr)
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{
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int difft = 8 - (int) strlen (ptr);
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while (difft > 0)
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{
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(*info->fprintf_func) (info->stream, "%c", ' ');
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difft -= 1;
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}
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}
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/* Process the R-type opcode. */
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static unsigned char
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dlx_r_type (struct disassemble_info *info)
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{
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unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
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int r_opc_num = (sizeof r_opc) / (sizeof (char));
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struct _r_opcode
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{
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unsigned long func;
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char *name;
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}
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dlx_r_opcode[] =
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{
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{ NOPF, "nop" }, /* NOP */
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{ ADDF, "add" }, /* Add */
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{ ADDUF, "addu" }, /* Add Unsigned */
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{ SUBF, "sub" }, /* SUB */
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{ SUBUF, "subu" }, /* Sub Unsigned */
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{ MULTF, "mult" }, /* MULTIPLY */
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{ MULTUF, "multu" }, /* MULTIPLY Unsigned */
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{ DIVF, "div" }, /* DIVIDE */
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{ DIVUF, "divu" }, /* DIVIDE Unsigned */
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{ ANDF, "and" }, /* AND */
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{ ORF, "or" }, /* OR */
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{ XORF, "xor" }, /* Exclusive OR */
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{ SLLF, "sll" }, /* SHIFT LEFT LOGICAL */
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{ SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */
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{ SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */
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{ SEQF, "seq" }, /* Set if equal */
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{ SNEF, "sne" }, /* Set if not equal */
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{ SLTF, "slt" }, /* Set if less */
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{ SGTF, "sgt" }, /* Set if greater */
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{ SLEF, "sle" }, /* Set if less or equal */
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{ SGEF, "sge" }, /* Set if greater or equal */
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{ SEQUF, "sequ" }, /* Set if equal */
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{ SNEUF, "sneu" }, /* Set if not equal */
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{ SLTUF, "sltu" }, /* Set if less */
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{ SGTUF, "sgtu" }, /* Set if greater */
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{ SLEUF, "sleu" }, /* Set if less or equal */
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{ SGEUF, "sgeu" }, /* Set if greater or equal */
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{ MVTSF, "mvts" }, /* Move to special register */
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{ MVFSF, "mvfs" }, /* Move from special register */
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{ BSWAPF, "bswap" }, /* Byte swap ?? */
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{ LUTF, "lut" } /* ????????? ?? */
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};
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int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
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int idx;
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for (idx = 0; idx < r_opc_num; idx++)
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{
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if (r_opc[idx] != opc)
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continue;
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else
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break;
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}
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if (idx == r_opc_num)
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return NIL;
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for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
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if (dlx_r_opcode[idx].func == func)
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);
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if (func != NOPF)
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{
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/* This is not a nop. */
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operand_deliminator (info, dlx_r_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d,", (int)rd);
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(*info->fprintf_func) (info->stream, "r%d", (int)rs1);
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if (func != MVTSF && func != MVFSF)
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(*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
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}
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return (unsigned char) R_TYPE;
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}
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return (unsigned char) R_ERROR;
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}
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/* Process the memory read opcode. */
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static unsigned char
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dlx_load_type (struct disassemble_info* info)
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{
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struct _load_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_load_opcode[] =
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{
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{ OPC(LHIOP), "lhi" }, /* Load HI to register. */
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{ OPC(LBOP), "lb" }, /* load byte sign extended. */
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{ OPC(LBUOP), "lbu" }, /* load byte unsigned. */
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{ OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
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{ OPC(LHOP), "lh" }, /* load halfword sign extended. */
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{ OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
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{ OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */
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{ OPC(LWOP), "lw" }, /* load word. */
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{ OPC(LSWOP), "ldstw" } /* load store word. */
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};
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int dlx_load_opcode_num =
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(sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
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if (dlx_load_opcode[idx].opcode == opc)
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{
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if (opc == OPC (LHIOP))
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
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operand_deliminator (info, dlx_load_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
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(*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
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}
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else
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
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operand_deliminator (info, dlx_load_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
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(*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
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}
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return (unsigned char) ILD_TYPE;
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}
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return (unsigned char) NIL;
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}
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/* Process the memory store opcode. */
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static unsigned char
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dlx_store_type (struct disassemble_info* info)
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{
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struct _store_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_store_opcode[] =
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{
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{ OPC(SBOP), "sb" }, /* Store byte. */
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{ OPC(SHOP), "sh" }, /* Store halfword. */
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{ OPC(SWOP), "sw" }, /* Store word. */
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};
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int dlx_store_opcode_num =
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(sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
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if (dlx_store_opcode[idx].opcode == opc)
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
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operand_deliminator (info, dlx_store_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
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(*info->fprintf_func) (info->stream, "r%d", (int)rs2);
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return (unsigned char) IST_TYPE;
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}
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return (unsigned char) NIL;
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}
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/* Process the Arithmetic and Logical I-TYPE opcode. */
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static unsigned char
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dlx_aluI_type (struct disassemble_info* info)
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{
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struct _aluI_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_aluI_opcode[] =
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{
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{ OPC(ADDIOP), "addi" }, /* Store byte. */
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{ OPC(ADDUIOP), "addui" }, /* Store halfword. */
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{ OPC(SUBIOP), "subi" }, /* Store word. */
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{ OPC(SUBUIOP), "subui" }, /* Store word. */
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{ OPC(ANDIOP), "andi" }, /* Store word. */
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{ OPC(ORIOP), "ori" }, /* Store word. */
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{ OPC(XORIOP), "xori" }, /* Store word. */
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{ OPC(SLLIOP), "slli" }, /* Store word. */
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{ OPC(SRAIOP), "srai" }, /* Store word. */
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{ OPC(SRLIOP), "srli" }, /* Store word. */
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{ OPC(SEQIOP), "seqi" }, /* Store word. */
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{ OPC(SNEIOP), "snei" }, /* Store word. */
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{ OPC(SLTIOP), "slti" }, /* Store word. */
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{ OPC(SGTIOP), "sgti" }, /* Store word. */
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{ OPC(SLEIOP), "slei" }, /* Store word. */
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{ OPC(SGEIOP), "sgei" }, /* Store word. */
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{ OPC(SEQUIOP), "sequi" }, /* Store word. */
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{ OPC(SNEUIOP), "sneui" }, /* Store word. */
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{ OPC(SLTUIOP), "sltui" }, /* Store word. */
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{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
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{ OPC(SLEUIOP), "sleui" }, /* Store word. */
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{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
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#if 0
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{ OPC(MVTSOP), "mvts" }, /* Store word. */
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{ OPC(MVFSOP), "mvfs" }, /* Store word. */
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#endif
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};
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int dlx_aluI_opcode_num =
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(sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
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if (dlx_aluI_opcode[idx].opcode == opc)
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
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operand_deliminator (info, dlx_aluI_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
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(*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
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(*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
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return (unsigned char) IAL_TYPE;
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}
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return (unsigned char) NIL;
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}
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/* Process the branch instruction. */
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static unsigned char
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dlx_br_type (struct disassemble_info* info)
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{
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struct _br_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_br_opcode[] =
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{
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{ OPC(BEQOP), "beqz" }, /* Store byte. */
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{ OPC(BNEOP), "bnez" } /* Store halfword. */
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};
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int dlx_br_opcode_num =
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(sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
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if (dlx_br_opcode[idx].opcode == opc)
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{
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if (imm16 & 0x00008000)
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imm16 |= 0xFFFF0000;
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imm16 += (current_insn_addr + 4);
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(*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
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operand_deliminator (info, dlx_br_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
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(*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
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return (unsigned char) IBR_TYPE;
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}
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return (unsigned char) NIL;
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}
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/* Process the jump instruction. */
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static unsigned char
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dlx_jmp_type (struct disassemble_info* info)
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{
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struct _jmp_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_jmp_opcode[] =
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{
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{ OPC(JOP), "j" }, /* Store byte. */
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{ OPC(JALOP), "jal" }, /* Store halfword. */
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{ OPC(BREAKOP), "break" }, /* Store halfword. */
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{ OPC(TRAPOP), "trap" }, /* Store halfword. */
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{ OPC(RFEOP), "rfe" } /* Store halfword. */
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};
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int dlx_jmp_opcode_num =
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(sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
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if (dlx_jmp_opcode[idx].opcode == opc)
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{
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if (imm26 & 0x02000000)
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imm26 |= 0xFC000000;
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imm26 += (current_insn_addr + 4);
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(*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
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operand_deliminator (info, dlx_jmp_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);
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return (unsigned char) IJ_TYPE;
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}
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return (unsigned char) NIL;
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}
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/* Process the jump register instruction. */
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static unsigned char
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dlx_jr_type (struct disassemble_info* info)
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{
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struct _jr_opcode
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{
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unsigned long opcode;
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char *name;
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}
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dlx_jr_opcode[] =
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{
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{ OPC(JROP), "jr" }, /* Store byte. */
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{ OPC(JALROP), "jalr" } /* Store halfword. */
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};
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int dlx_jr_opcode_num =
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(sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
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int idx;
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for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
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if (dlx_jr_opcode[idx].opcode == opc)
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{
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(*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
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operand_deliminator (info, dlx_jr_opcode[idx].name);
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(*info->fprintf_func) (info->stream, "r%d", (int)rs1);
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return (unsigned char) IJR_TYPE;
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}
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return (unsigned char) NIL;
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}
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typedef unsigned char (* dlx_insn) (struct disassemble_info *);
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/* This is the main DLX insn handling routine. */
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int
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print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
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{
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bfd_byte buffer[4];
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int insn_idx;
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unsigned long insn_word;
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dlx_insn dlx_insn_type[] =
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{
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dlx_r_type,
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dlx_load_type,
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dlx_store_type,
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dlx_aluI_type,
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dlx_br_type,
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dlx_jmp_type,
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dlx_jr_type,
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(dlx_insn) NULL
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};
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int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1;
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int status =
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(*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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/* Now decode the insn */
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insn_word = bfd_getb32 (buffer);
|
|
opc = dlx_get_opcode (insn_word);
|
|
rs1 = dlx_get_rs1 (insn_word);
|
|
rs2 = dlx_get_rs2 (insn_word);
|
|
rd = dlx_get_rdR (insn_word);
|
|
func = dlx_get_func (insn_word);
|
|
imm16= dlx_get_imm16 (insn_word);
|
|
imm26= dlx_get_imm26 (insn_word);
|
|
|
|
#if 0
|
|
printf ("print_insn_big_dlx: opc = 0x%02x\n"
|
|
" rs1 = 0x%02x\n"
|
|
" rs2 = 0x%02x\n"
|
|
" rd = 0x%02x\n"
|
|
" func = 0x%08x\n"
|
|
" imm16 = 0x%08x\n"
|
|
" imm26 = 0x%08x\n",
|
|
opc, rs1, rs2, rd, func, imm16, imm26);
|
|
#endif
|
|
|
|
/* Scan through all the insn type and print the insn out. */
|
|
current_insn_addr = (unsigned long) memaddr;
|
|
|
|
for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
|
|
switch ((dlx_insn_type[insn_idx]) (info))
|
|
{
|
|
/* Found the correct opcode */
|
|
case R_TYPE:
|
|
case ILD_TYPE:
|
|
case IST_TYPE:
|
|
case IAL_TYPE:
|
|
case IBR_TYPE:
|
|
case IJ_TYPE:
|
|
case IJR_TYPE:
|
|
return 4;
|
|
|
|
/* Wrong insn type check next one. */
|
|
default:
|
|
case NIL:
|
|
continue;
|
|
|
|
/* All rest of the return code are not recongnized, treat it as error */
|
|
/* we should never get here, I hope! */
|
|
case R_ERROR:
|
|
return -1;
|
|
}
|
|
|
|
if (insn_idx == dlx_insn_type_num)
|
|
/* Well, does not recoganize this opcode. */
|
|
(*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");
|
|
|
|
return 4;
|
|
}
|