mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
dbbb1059e6
This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
121 lines
4.1 KiB
Plaintext
121 lines
4.1 KiB
Plaintext
# Copyright 2003-2018 Free Software Foundation, Inc.
|
|
|
|
# This program is free software; you can redistribute it and/or modify
|
|
# it under the terms of the GNU General Public License as published by
|
|
# the Free Software Foundation; either version 3 of the License, or
|
|
# (at your option) any later version.
|
|
#
|
|
# This program is distributed in the hope that it will be useful,
|
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
# GNU General Public License for more details.
|
|
#
|
|
# You should have received a copy of the GNU General Public License
|
|
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
# Please email any bugs, comments, and/or additions to this file to:
|
|
# bug-gdb@gnu.org
|
|
|
|
# This file is part of the gdb testsuite.
|
|
|
|
#
|
|
# Test floating-point related functionality.
|
|
#
|
|
|
|
|
|
if { [prepare_for_testing "failed to prepare" float float.c] } {
|
|
return -1
|
|
}
|
|
|
|
# Set it up at a breakpoint so we have its registers.
|
|
|
|
if ![runto_main] then {
|
|
perror "couldn't run to breakpoint"
|
|
continue
|
|
}
|
|
|
|
# Test "info float".
|
|
|
|
if { [is_aarch64_target] } then {
|
|
gdb_test "info float" "d0.*d1.*d31.*s0.*s1.*s31.*" "info float"
|
|
} elseif { [istarget "alpha*-*-*"] } then {
|
|
gdb_test "info float" "f0.*" "info float"
|
|
} elseif { [is_aarch32_target] } then {
|
|
gdb_test_multiple "info float" "info float" {
|
|
-re "Software FPU type.*mask:.*flags:.*$gdb_prompt $" {
|
|
pass "info float (FPA)"
|
|
}
|
|
-re "fpscr.*s0.*s1.*s31.*$gdb_prompt $" {
|
|
# Only check for single precision; d0 might be a vector register
|
|
# if we have NEON.
|
|
pass "info float (VFP)"
|
|
}
|
|
-re "No floating.point info available for this processor.*$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
}
|
|
} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } then {
|
|
gdb_test "info float" "R7:.*Status Word:.*Opcode:.*" "info float"
|
|
} elseif [istarget "ia64-*-*"] then {
|
|
gdb_test "info float" "f0.*f1.*f127.*" "info float"
|
|
} elseif [istarget "m68k-*-*"] then {
|
|
gdb_test_multiple "info float" "info_float" {
|
|
-re "fp0.*fp1.*fp7.*$gdb_prompt $" {
|
|
pass "info float (with FPU)"
|
|
}
|
|
-re "No floating.point info available for this processor.*$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
}
|
|
} elseif [istarget "mips*-*-*"] then {
|
|
gdb_test_multiple "info float" "info float" {
|
|
-re "fpu type: none / unused\r\n$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
-re "fpu type:.*cause.*mask.*flags.*round.*flush.*f0:.*flt:.*dbl:.*$gdb_prompt $" {
|
|
pass "info float (with FPU)"
|
|
}
|
|
}
|
|
} elseif [istarget "nds32*-*-*"] then {
|
|
gdb_test_multiple "info float" "info_float" {
|
|
-re "fd0.*fd3.*$gdb_prompt $" {
|
|
pass "info float (with FPU)"
|
|
}
|
|
-re "No floating.point info available for this processor.*$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
}
|
|
} elseif [istarget "powerpc*-*-*"] then {
|
|
gdb_test_multiple "info float" "info_float" {
|
|
-re "f0.*f1.*f31.*fpscr.*$gdb_prompt $" {
|
|
pass "info float (with FPU)"
|
|
}
|
|
-re "No floating.point info available for this processor.*$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
}
|
|
} elseif [istarget "s390*-*-*"] then {
|
|
gdb_test "info float" "fpc.*f0.*f1.*f15.*" "info float"
|
|
} elseif [istarget "sh*-*"] then {
|
|
# SH may or may not have an FPU
|
|
gdb_test_multiple "info float" "info float" {
|
|
-re "fpul.*fr0.*fr1.*fr15.*$gdb_prompt $" {
|
|
pass "info float (with FPU)"
|
|
}
|
|
-re "No floating.point info available for this processor.*$gdb_prompt $" {
|
|
pass "info float (without FPU)"
|
|
}
|
|
}
|
|
} elseif [istarget "hppa*-*"] then {
|
|
gdb_test "info float" "fr4.*fr4R.*fr31R.*" "info float"
|
|
} elseif [istarget "sparc*-*-*"] then {
|
|
gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
|
|
} elseif [istarget "riscv*-*-*"] then {
|
|
gdb_test "info float" "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*" "info float"
|
|
} else {
|
|
gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)"
|
|
}
|
|
|
|
gdb_test "step"
|
|
gdb_test "finish" "Value returned is .* = (inf|nan).*"
|