Richard Earnshaw ad5da6e6d8 arm: opcodes: remove Maverick disassembly. ... Remove the patterns to match Maverick co-processor instructions from the disassembly tables. This required fixing a couple of tests in the assembler testsuite where we, probably incorrectly, disassembled generic co-processor instructions as a Maverick instruction (it particularly made no sense to do this for Armv6t2 in Thumb state).		2024-05-14 10:56:58 +01:00
..
aarch64.h	aarch64: Remove asserts from operand qualifier decoders [PR31595]	2024-04-17 11:18:55 +01:00
alpha.h
arc-attrs.h
arc-func.h
arc.h	arc: Put DBNZ instruction to a separate class	2024-02-14 11:36:52 +01:00
arm.h	arm: opcodes: remove Maverick disassembly.	2024-05-14 10:56:58 +01:00
avr.h
bfin.h
bpf.h	bpf: there is no ldinddw nor ldabsdw instructions	2024-01-29 19:22:41 +01:00
cgen.h
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
csky.h
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h
ia64.h
kvx.h	kvx: gas: rename: or -> ior, xor -> eor	2024-02-20 12:07:57 +01:00
loongarch.h	LoongArch: Add -mignore-start-align option	2024-04-20 12:10:40 +08:00
m68hc11.h
m68k.h
metag.h
mips.h
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h
pru.h
pyr.h
riscv-opc.h	RISC-V: Support Zcmp push/pop instructions.	2024-04-09 15:56:12 +08:00
riscv.h	RISC-V: Support B, Zaamo and Zalrsc extensions.	2024-05-08 12:34:58 +08:00
rl78.h
rx.h
s12z.h
s390.h	s390: Warn when register name type does not match operand	2024-03-01 12:45:14 +01:00
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tilegx.h
tilepro.h
v850.h
vax.h
visium.h
wasm.h
xgate.h