binutils-gdb/cpu
Jose E. Marchesi 78c1c35437 cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes
This patch adds semantic RTL descriptions to the eBPF instructions
defined in cpu/bpf.cpu.  It also contains a couple of minor
improvements.

Tested in bpf-unknown-none targets.
No regressions.

cpu/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
	(define-alu-insn-mov): Likewise.
	(daib): Likewise.
	(define-alu-instructions): Likewise.
	(define-endian-insn): Likewise.
	(define-lddw): Likewise.
	(dlabs): Likewise.
	(dlind): Likewise.
	(dxli): Likewise.
	(dxsi): Likewise.
	(dsti): Likewise.
	(define-ldstx-insns): Likewise.
	(define-st-insns): Likewise.
	(define-cond-jump-insn): Likewise.
	(dcji): Likewise.
	(define-condjump-insns): Likewise.
	(define-call-insn): Likewise.
	(ja): Likewise.
	("exit"): Likewise.
	(define-atomic-insns): Likewise.
	(sem-exchange-and-add): New macro.
	* bpf.cpu ("brkpt"): New instruction.
	(bpfbf): Set word-bitsize to 32 and insn-endian big.
	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
	(h-pc): Expand definition.
	* bpf.opc (bpf_print_insn): Set endian_code to BIG.

opcodes/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-05-28 21:52:31 +02:00
..
bpf.cpu cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes 2020-05-28 21:52:31 +02:00
bpf.opc cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes 2020-05-28 21:52:31 +02:00
ChangeLog cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes 2020-05-28 21:52:31 +02:00
cris.cpu
epiphany.cpu Remove more shifts for sign/zero extension 2019-12-11 21:14:19 +10:30
epiphany.opc
fr30.cpu ubsan: fr30: left shift of negative value 2020-01-13 12:12:05 +10:30
fr30.opc
frv.cpu ubsan: frv: left shift of negative value 2020-02-01 23:23:18 +10:30
frv.opc
ip2k.cpu
ip2k.opc
iq10.cpu
iq2000.cpu ubsan: iq2000: left shift of negative value 2019-12-23 18:04:12 +10:30
iq2000.opc
iq2000m.cpu
lm32.cpu Remove more shifts for sign/zero extension 2019-12-11 21:14:19 +10:30
lm32.opc
m32c.cpu ubsan: m32c: left shift of negative value 2020-02-03 15:59:08 +10:30
m32c.opc
m32r.cpu ubsan: m32r: left shift of negative value 2020-01-04 19:20:33 +10:30
m32r.opc
mep-avc2.cpu
mep-avc.cpu
mep-c5.cpu
mep-core.cpu
mep-default.cpu
mep-ext-cop.cpu
mep-fmax.cpu
mep-h1.cpu
mep-ivc2.cpu
mep-rhcop.cpu
mep-sample-ucidsp.cpu
mep.cpu
mep.opc Replace "if (x) free (x)" with "free (x)", opcodes 2020-05-21 10:45:33 +09:30
mt.cpu
mt.opc
or1k.cpu or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts 2020-05-19 20:40:27 +09:00
or1k.opc cpu/or1k: Add support for orfp64a32 spec 2019-06-13 06:16:18 +09:00
or1kcommon.cpu or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts 2020-05-19 20:40:27 +09:00
or1korbis.cpu ubsan: or1k: left shift of negative value 2019-12-20 17:57:58 +10:30
or1korfpx.cpu or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts 2020-05-19 20:40:27 +09:00
sh64-compact.cpu
sh64-media.cpu
sh.cpu
sh.opc
simplify.inc
xc16x.cpu
xc16x.opc
xstormy16.cpu ubsan: xstormy16: left shift of negative value 2019-12-16 17:35:13 +10:30
xstormy16.opc