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abe9f67d45
binutils/opcodes
* microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
* microblaze-opcm.h (microblaze_instr): Likewise
binutils/gas/testsuite
* gas/microblaze/allinsn.s: Add swapb, swaph
* gas/microblaze/allinsn.d: Likewise
149 lines
5.4 KiB
C
149 lines
5.4 KiB
C
/* microblaze-opcm.h -- Header used in microblaze-opc.h
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Copyright 2009 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef MICROBLAZE_OPCM
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#define MICROBLAZE_OPCM
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enum microblaze_instr
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{
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add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
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addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
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mulh, mulhu, mulhsu,swapb,swaph,
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idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
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ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
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andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
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wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
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brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
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bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
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imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
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brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
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bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
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shr, sw, swr, swx, lbui, lhui, lwi,
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sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
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fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
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fint, fsqrt,
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tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
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eget, ecget, neget, necget, eput, ecput, neput, necput,
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teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
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aget, caget, naget, ncaget, aput, caput, naput, ncaput,
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taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
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eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
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teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
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getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
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putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
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egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
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eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
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agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
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aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
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eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
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eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
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invalid_inst
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};
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enum microblaze_instr_type
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{
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arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
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return_inst, immediate_inst, special_inst, memory_load_inst,
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memory_store_inst, barrel_shift_inst, anyware_inst
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};
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#define INST_WORD_SIZE 4
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/* Gen purpose regs go from 0 to 31. */
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/* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */
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#define REG_PC_MASK 0x8000
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#define REG_MSR_MASK 0x8001
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#define REG_EAR_MASK 0x8003
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#define REG_ESR_MASK 0x8005
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#define REG_FSR_MASK 0x8007
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#define REG_BTR_MASK 0x800b
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#define REG_EDR_MASK 0x800d
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#define REG_PVR_MASK 0xa000
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#define REG_SLR_MASK 0x8800
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#define REG_SHR_MASK 0x8802
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#define REG_PID_MASK 0x9000
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#define REG_ZPR_MASK 0x9001
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#define REG_TLBX_MASK 0x9002
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#define REG_TLBLO_MASK 0x9003
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#define REG_TLBHI_MASK 0x9004
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#define REG_TLBSX_MASK 0x9005
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#define MIN_REGNUM 0
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#define MAX_REGNUM 31
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#define MIN_PVR_REGNUM 0
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#define MAX_PVR_REGNUM 15
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#define REG_PC 32 /* PC. */
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#define REG_MSR 33 /* Machine status reg. */
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#define REG_EAR 35 /* Exception reg. */
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#define REG_ESR 37 /* Exception reg. */
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#define REG_FSR 39 /* FPU Status reg. */
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#define REG_BTR 43 /* Branch Target reg. */
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#define REG_EDR 45 /* Exception reg. */
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#define REG_SHR 50 /* Stack High reg. */
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#define REG_SLR 51 /* Stack Low reg. */
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#define REG_PVR 40960 /* Program Verification reg. */
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#define REG_PID 36864 /* MMU: Process ID reg. */
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#define REG_ZPR 36865 /* MMU: Zone Protect reg. */
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#define REG_TLBX 36866 /* MMU: TLB Index reg. */
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#define REG_TLBLO 36867 /* MMU: TLB Low reg. */
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#define REG_TLBHI 36868 /* MMU: TLB High reg. */
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#define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */
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/* Alternate names for gen purpose regs. */
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#define REG_SP 1 /* stack pointer. */
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#define REG_ROSDP 2 /* read-only small data pointer. */
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#define REG_RWSDP 13 /* read-write small data pointer. */
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/* Assembler Register - Used in Delay Slot Optimization. */
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#define REG_AS 18
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#define REG_ZERO 0
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#define RD_LOW 21 /* Low bit for RD. */
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#define RA_LOW 16 /* Low bit for RA. */
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#define RB_LOW 11 /* Low bit for RB. */
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#define IMM_LOW 0 /* Low bit for immediate. */
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#define IMM_MBAR 21 /* low bit for mbar instruction. */
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#define RD_MASK 0x03E00000
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#define RA_MASK 0x001F0000
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#define RB_MASK 0x0000F800
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#define IMM_MASK 0x0000FFFF
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/* Imm mask for barrel shifts. */
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#define IMM5_MASK 0x0000001F
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/* Imm mask for mbar. */
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#define IMM5_MBAR_MASK 0x03E00000
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/* FSL imm mask for get, put instructions. */
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#define RFSL_MASK 0x000000F
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/* Imm mask for msrset, msrclr instructions. */
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#define IMM15_MASK 0x00007FFF
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#endif /* MICROBLAZE-OPCM */
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