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https://sourceware.org/git/binutils-gdb.git
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ab25d9bbe4
After the commit:
commit 08106042d9
Date: Thu May 19 13:20:17 2022 +0100
gdb: move the type cast into gdbarch_tdep
GDB would no longer build using g++ 4.8. The issue appears to be some
confusion caused by GDB having 'struct gdbarch_tdep', but also a
templated function called 'gdbarch_tdep'. Prior to the above commit
the gdbarch_tdep function was not templated, and this compiled just
fine. Note that the above commit compiles just fine with later
versions of g++, so this issue was clearly fixed at some point, though
I've not tried to track down exactly when.
In this commit I propose to fix the g++ 4.8 build problem by renaming
'struct gdbarch_tdep' to 'struct gdbarch_tdep_base'. This rename
better represents that the struct is only ever used as a base class,
and removes the overloading of the name, which allows GDB to build
with g++ 4.8.
I've also updated the comment on 'struct gdbarch_tdep_base' to fix a
typo, and the comment on the 'gdbarch_tdep' function, to mention that
in maintainer mode a run-time type check is performed.
178 lines
6.9 KiB
C++
178 lines
6.9 KiB
C++
/* Target-dependent header for the RISC-V architecture, for GDB, the
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GNU Debugger.
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Copyright (C) 2018-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_TDEP_H
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#define RISCV_TDEP_H
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#include "arch/riscv.h"
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#include "gdbarch.h"
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/* RiscV register numbers. */
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enum
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{
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RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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RISCV_RA_REGNUM = 1, /* Return Address. */
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RISCV_SP_REGNUM = 2, /* Stack Pointer. */
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RISCV_GP_REGNUM = 3, /* Global Pointer. */
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RISCV_TP_REGNUM = 4, /* Thread Pointer. */
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_A7_REGNUM = 17, /* Seventh argument. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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RISCV_NUM_INTEGER_REGS = 32,
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
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RISCV_FA0_REGNUM = 43,
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RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
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RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
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RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
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#define DECLARE_CSR(name, num, class, define_version, abort_version) \
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RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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RISCV_LAST_CSR_REGNUM = 4160,
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RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
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RISCV_PRIV_REGNUM = 4161,
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RISCV_V0_REGNUM,
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RISCV_V31_REGNUM = RISCV_V0_REGNUM + 31,
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RISCV_LAST_REGNUM = RISCV_V31_REGNUM
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};
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/* RiscV DWARF register numbers. */
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enum
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{
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RISCV_DWARF_REGNUM_X0 = 0,
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RISCV_DWARF_REGNUM_X31 = 31,
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RISCV_DWARF_REGNUM_F0 = 32,
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RISCV_DWARF_REGNUM_F31 = 63,
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RISCV_DWARF_REGNUM_V0 = 96,
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RISCV_DWARF_REGNUM_V31 = 127,
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RISCV_DWARF_FIRST_CSR = 4096,
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RISCV_DWARF_LAST_CSR = 8191,
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};
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/* RISC-V specific per-architecture information. */
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struct riscv_gdbarch_tdep : gdbarch_tdep_base
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{
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/* Features about the target hardware that impact how the gdbarch is
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configured. Two gdbarch instances are compatible only if this field
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matches. */
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struct riscv_gdbarch_features isa_features;
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/* Features about the abi that impact how the gdbarch is configured. Two
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gdbarch instances are compatible only if this field matches. */
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struct riscv_gdbarch_features abi_features;
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/* ISA-specific data types. */
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struct type *riscv_fpreg_d_type = nullptr;
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/* Use for tracking unknown CSRs in the target description.
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UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
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CSR. All other unknown CSRs will be assigned sequential numbers after
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this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs. */
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int unknown_csrs_first_regnum = -1;
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int unknown_csrs_count = 0;
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/* Some targets (QEMU) are reporting three registers twice in the target
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description they send. These three register numbers, when not set to
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-1, are for the duplicate copies of these registers. */
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int duplicate_fflags_regnum = -1;
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int duplicate_frm_regnum = -1;
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int duplicate_fcsr_regnum = -1;
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/* Return the expected next PC assuming FRAME is stopped at a syscall
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instruction. */
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CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr;
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};
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/* Return the width in bytes of the general purpose registers for GDBARCH.
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Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
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RV128. */
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extern int riscv_isa_xlen (struct gdbarch *gdbarch);
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/* Return the width in bytes of the hardware floating point registers for
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GDBARCH. If this architecture has no floating point registers, then
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return 0. Possible values are 4, 8, or 16 for depending on which of
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single, double or quad floating point support is available. */
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extern int riscv_isa_flen (struct gdbarch *gdbarch);
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/* Return the width in bytes of the general purpose register abi for
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GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
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how the binary was compiled rather than the hardware that is available.
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It is possible that a binary compiled for RV32 is being run on an RV64
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target, in which case the isa xlen is 8-bytes, and the abi xlen is
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4-bytes. This will impact how inferior functions are called. */
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extern int riscv_abi_xlen (struct gdbarch *gdbarch);
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/* Return the width in bytes of the floating point register abi for
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GDBARCH. This reflects how the binary was compiled rather than the
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hardware that is available. It is possible that a binary is compiled
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for single precision floating point, and then run on a target with
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double precision floating point. A return value of 0 indicates that no
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floating point abi is in use (floating point arguments will be passed
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in integer registers) other possible return value are 4, 8, or 16 as
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with RISCV_ISA_FLEN. */
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extern int riscv_abi_flen (struct gdbarch *gdbarch);
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/* Return true if GDBARCH is using the embedded x-regs abi, that is the
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target only has 16 x-registers, which includes a reduced number of
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argument registers. */
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extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
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/* Single step based on where the current instruction will take us. */
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extern std::vector<CORE_ADDR> riscv_software_single_step
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(struct regcache *regcache);
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/* Supply register REGNUM from the buffer REGS (length LEN) into
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REGCACHE. REGSET describes the layout of the buffer. If REGNUM is -1
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then all registers described by REGSET are supplied.
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The register RISCV_ZERO_REGNUM should not be described by REGSET,
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however, this register (which always has the value 0) will be supplied
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by this function if requested.
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The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
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not be described by REGSET, however, these register will be provided if
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requested assuming either:
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(a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
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(b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
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buffer.
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This function can be used as the supply function for either x-regs or
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f-regs when loading corefiles, and doesn't care which abi is currently
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in use. */
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extern void riscv_supply_regset (const struct regset *regset,
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struct regcache *regcache, int regnum,
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const void *regs, size_t len);
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/* The names of the RISC-V target description features. */
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extern const char *riscv_feature_name_csr;
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#endif /* RISCV_TDEP_H */
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