mirror of
https://sourceware.org/git/binutils-gdb.git
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42a4f53d2b
This commit applies all changes made after running the gdb/copyright.py script. Note that one file was flagged by the script, due to an invalid copyright header (gdb/unittests/basic_string_view/element_access/char/empty.cc). As the file was copied from GCC's libstdc++-v3 testsuite, this commit leaves this file untouched for the time being; a patch to fix the header was sent to gcc-patches first. gdb/ChangeLog: Update copyright year range in all GDB files.
213 lines
5.9 KiB
Plaintext
213 lines
5.9 KiB
Plaintext
# Copyright 2015-2019 Free Software Foundation, Inc.
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# Test vector register access for s390 platforms.
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if { ![istarget s390-*-*] && ![istarget s390x-*-* ] } {
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verbose "Skipping s390 vector register tests."
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return
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}
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standard_testfile .S
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if [isnative] {
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# Create a temporary directory, to take a core dump there later.
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set coredir [standard_output_file ${testfile}.d]
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remote_exec build "rm -rf $coredir"
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remote_exec build "mkdir $coredir"
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}
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if { [prepare_for_testing "failed to prepare" $testfile $srcfile \
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[list "additional_flags=-mzarch"]] } {
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return -1
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}
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if ![runto_main] {
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untested "could not run to main"
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return -1
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}
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# Run to the first vector instruction and step it. If the inferior
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# doesn't crash, we have vector support.
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gdb_breakpoint "check_vx"
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gdb_continue_to_breakpoint "first vector insn"
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set before_pc 0
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gdb_test_multiple "x/i \$pc" "get PC at vector insn" {
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-re "(0x\\S+)\\s+\\S+\\s+vlr\\s+.*$gdb_prompt $" {
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set before_pc $expect_out(1,string)
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}
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}
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gdb_test_multiple "stepi" "check for vector support" {
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-re "Program received signal SIGILL,.*\r\n$gdb_prompt $" {
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unsupported "no vector support."
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return
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}
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-re "\[0-9\]+.*\r\n$gdb_prompt $" {
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pass "vector support available"
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}
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-re "$gdb_prompt $" {
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fail "no vector support (unknown error)"
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return
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}
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}
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# Has the PC advanced by the expected amount? The kernel may do
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# something special for the first vector insn in the process.
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set after_pc 0
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gdb_test_multiple "x/i \$pc" "get PC after vector insn" {
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-re "(0x\\S+)\\s+.*$gdb_prompt $" {
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set after_pc $expect_out(1,string)
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}
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}
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if [expr $before_pc + 6 != $after_pc] {
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fail "stepping first vector insn"
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}
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# Lift the core file limit, if possible, and change into the temporary
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# directory.
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if { $coredir != "" } {
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gdb_test {print (int) setrlimit (4, &(unsigned long [2]){~0UL, ~0UL})} \
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" = .*" "setrlimit"
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gdb_test "print (int) chdir (\"${coredir}\")" " = 0" "chdir"
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}
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# Initialize all vector registers with GDB "set" commands, using
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# distinct values. Handle left and right halves separately, in
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# pseudo-random order.
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set a_high 1
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set a_low 2
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set b_high 3
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set b_low 5
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set a [expr ($a_high << 32) | $a_low]
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set b [expr ($b_high << 32) | $b_low]
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for {set j 0} {$j < 32} {incr j 1} {
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set i [expr 17 * $j % 32]
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gdb_test_no_output \
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"set \$v$i.v2_int64\[0\] = [expr $a * ($i + 1)]" \
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"set v$i left"
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set i [expr 19 * (31 - $j) % 32]
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gdb_test_no_output \
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"set \$v$i.v2_int64\[1\] = [expr $b * (32 - $i)]" \
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"set v$i right"
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}
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# Verify a vector register's union members.
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gdb_test "info register v0 v31" \
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"v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128\
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.*v4_float .* v2_double .* v16_int8 .* v8_int16 .* v4_int32 .* v2_int64 .* uint128 .*"
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# Let the inferior store all vector registers in a buffer, then dump
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# the buffer and check it.
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gdb_continue_to_breakpoint "store vrs"
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set vregs [capture_command_output "x/64xg &save_area" ""]
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set i 0
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foreach {- left right} [regexp -all -inline -line {^.*:\s+(\w+)\s+(\w+)} $vregs] {
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if [expr $left != $a * ($i + 1) || $right != $b * (32 - $i)] {
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fail "verify \$v$i after set"
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}
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if { $i < 16 } {
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# Check that the FP register was updated accordingly.
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gdb_test "info register f$i" "raw ${left}.*"
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}
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incr i 1
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}
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if { $i != 32 } {
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fail "dump save area (bad output)"
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}
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# Let the inferior change all VRs according to a simple algorithm,
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# then print all VRs and compare their values with our result of the
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# same algorithm.
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gdb_continue_to_breakpoint "change vrs"
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set vregs [capture_command_output "info registers vector" ""]
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# Format a 128-bit value, given individual 4-byte values, as hex.
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# Suppress leading zeros.
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proc hex128 {a_high a_low b_high b_low} {
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set result [format "%x%08x%08x%08x" $a_high $a_low $b_high $b_low]
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regsub -- "^0*" $result "" result
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if { $result eq "" } { set result 0 }
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return $result
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}
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set j 1
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foreach {- r i val} [regexp -all -inline -line \
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{^(\D*)(\d+)\s+.*?uint128 = 0x([0-9a-f]+?)} $vregs] {
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if { $r ne "v" } {
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fail "info registers vector: bad line $j"
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} elseif { $val ne [hex128 \
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[expr $a_high * ($i + 1) * $a_high ] \
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[expr $a_low * ($i + 1) * $a_low ] \
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[expr $b_high * (32 - $i) * $b_high * 32] \
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[expr $b_low * (32 - $i) * $b_low * 32] ] } {
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fail "compare \$v$i"
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}
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incr j 1
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}
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if { $j != 33 } {
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fail "info registers vector"
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}
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if { $coredir == "" } {
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return
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}
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# Take a core dump.
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gdb_test "signal SIGABRT" "Program terminated with signal SIGABRT, .*"
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gdb_exit
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# Find the core file and rename it (avoid accumulating core files).
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set cores [glob -nocomplain -directory $coredir *core*]
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if {[llength $cores] != 1} {
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untested "core file not found"
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remote_exec build "rm -rf $coredir"
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return -1
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}
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set destcore [standard_output_file ${testfile}.core]
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remote_exec build "mv [file join $coredir [lindex $cores 0]] $destcore"
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remote_exec build "rm -rf $coredir"
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# Restart gdb and load the core file. Compare the VRs.
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clean_restart ${testfile}
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with_test_prefix "core" {
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set core_loaded [gdb_core_cmd $destcore "load"]
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if { $core_loaded != -1 } {
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set vregs_from_core [capture_command_output "info registers vector" ""]
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if { $vregs_from_core eq $vregs } {
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pass "compare vector registers"
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} else {
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fail "vector registers mismatch"
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}
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}
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}
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