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b4e87f2c1e
We currently use a padding NOP after a Thumb to Arm interworking veneer (BX pc). The NOP is never executed but may result in a performance penalty on some cores. For this reason this patch changes the NOPs after Thumb to Arm veneers into B .-2 and adds a note to this in the source code for future reference. bfd/ChangeLog: * elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub, elf32_arm_stub_long_branch_v4t_thumb_thumb, elf32_arm_stub_long_branch_v4t_thumb_arm, elf32_arm_stub_short_branch_v4t_thumb_arm, elf32_arm_stub_long_branch_v4t_thumb_arm_pic, elf32_arm_stub_long_branch_v4t_thumb_thumb_pic, elf32_arm_stub_long_branch_v4t_thumb_tls_pic): Change nop to branch to previous instruction. ld/ChangeLog: * testsuite/ld-arm/cortex-a8-fix-b-plt.d: Update Testcase. * testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * testsuite/ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * testsuite/ld-arm/farcall-cond-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-mixed-app.d: Likewise. * testsuite/ld-arm/farcall-mixed-app2.d: Likewise. * testsuite/ld-arm/farcall-mixed-lib-v4t.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * testsuite/ld-arm/fix-arm1176-on.d: Likewise. * testsuite/ld-arm/ifunc-10.dd: Likewise. * testsuite/ld-arm/ifunc-2.dd: Likewise. * testsuite/ld-arm/ifunc-4.dd: Likewise. * testsuite/ld-arm/ifunc-6.dd: Likewise. * testsuite/ld-arm/ifunc-8.dd: Likewise. * testsuite/ld-arm/jump-reloc-veneers-long.d: Likewise. * testsuite/ld-arm/mixed-app.d: Likewise. * testsuite/ld-arm/thumb2-b-interwork.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise. * testsuite/ld-arm/tls-thumb1.d: Likewise.
75 lines
1.9 KiB
Makefile
75 lines
1.9 KiB
Makefile
.*: file format elf32-.*arm
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architecture: arm.*, flags 0x00000150:
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HAS_SYMS, DYNAMIC, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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0000813c <.plt>:
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.*: e52de004 push {lr} ; .*
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.*: e59fe004 ldr lr, \[pc, #4\] ; .*
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.*: e08fe00e add lr, pc, lr
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.*: e5bef008 ldr pc, \[lr, #8\]!
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.*: 000080f0 .word 0x000080f0
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.*: e08e0000 add r0, lr, r0
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.*: e5901004 ldr r1, \[r0, #4\]
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.*: e12fff11 bx r1
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.*: e52d2004 push {r2} ; .*
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.*: e59f200c ldr r2, \[pc, #12\] ; .*
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.*: e59f100c ldr r1, \[pc, #12\] ; .*
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.*: e79f2002 ldr r2, \[pc, r2\]
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.*: e081100f add r1, r1, pc
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.*: e12fff12 bx r2
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.*: 000080e8 .word 0x000080e8
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.*: 000080c8 .word 0x000080c8
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Disassembly of section .text:
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00008180 <text>:
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: ebfffff1 bl .* <\.plt\+0x14>
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.*: e1a00000 nop ; .*
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.*: 000080c0 .word 0x000080c0
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.*: 4801 ldr r0, \[pc, #4\] ; .*
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.*: f000 f805 bl .* <__unnamed_veneer>
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.*: 46c0 nop ; .*
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.*: 000080b1 .word 0x000080b1
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.*: 00000000 .word 0x00000000
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000081a0 <__unnamed_veneer>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59f1000 ldr r1, \[pc\] ; .*
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.*: e081f00f add pc, r1, pc
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.*: ffffffa0 .word 0xffffffa0
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Disassembly of section .foo:
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04001000 <foo>:
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: eb000009 bl 4001030 .*
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.*: e1a00000 nop ; .*
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.*: fc00f240 .word 0xfc00f240
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: eb000005 bl 4001030 .*
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.*: e1a00000 nop ; .*
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.*: fc00f238 .word 0xfc00f238
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.*: 4801 ldr r0, \[pc, #4\] ; .*
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.*: f000 f80b bl 400103c .*
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.*: 46c0 nop ; .*
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.*: fc00f221 .word 0xfc00f221
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.*: 00000000 .word 0x00000000
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04001030 <__unnamed_veneer>:
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.*: e59f1000 ldr r1, \[pc\] ; .*
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.*: e08ff001 add pc, pc, r1
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.*: fc007114 .word 0xfc007114
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0400103c <__unnamed_veneer>:
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.*: 4778 bx pc
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.*: e7fd b.n .+ <.+>
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.*: e59f1000 ldr r1, \[pc\] ; .*
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.*: e081f00f add pc, r1, pc
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.*: fc007104 .word 0xfc007104
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.*: 00000000 .word 0x00000000
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