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11115521f6
pending interrupts. * interrupts.c (interrupts_process): Keep track of the last number of masked insn cycles. (interrupts_initialize): Clear last number of masked insn cycles. (interrupts_info): Report them. (interrupts_update_pending): Compute clear and set masks of interrupts and clear the interrupt bits before setting them (due to SCI interrupt sharing). * interrupts.h (struct interrupts): New members last_mask_cycles and xirq_last_mask_cycles.
346 lines
11 KiB
C
346 lines
11 KiB
C
/* interrupts.c -- 68HC11 Interrupts Emulation
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Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@worldnet.fr)
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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struct interrupt_def idefs[] = {
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/* Serial interrupts. */
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{ M6811_INT_SCI, M6811_SCSR, M6811_TDRE, M6811_SCCR2, M6811_TIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_TC, M6811_SCCR2, M6811_TCIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_RDRF, M6811_SCCR2, M6811_RIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_IDLE, M6811_SCCR2, M6811_ILIE },
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/* SPI interrupts. */
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{ M6811_INT_SPI, M6811_SPSR, M6811_SPIF, M6811_SPCR, M6811_SPIE },
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/* Realtime interrupts. */
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{ M6811_INT_TCTN, M6811_TFLG2, M6811_TOF, M6811_TMSK2, M6811_TOI },
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{ M6811_INT_RT, M6811_TFLG2, M6811_RTIF, M6811_TMSK2, M6811_RTII },
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/* Output compare interrupts. */
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{ M6811_INT_OUTCMP1, M6811_TFLG1, M6811_OC1F, M6811_TMSK1, M6811_OC1I },
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{ M6811_INT_OUTCMP2, M6811_TFLG1, M6811_OC2F, M6811_TMSK1, M6811_OC2I },
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{ M6811_INT_OUTCMP3, M6811_TFLG1, M6811_OC3F, M6811_TMSK1, M6811_OC3I },
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{ M6811_INT_OUTCMP4, M6811_TFLG1, M6811_OC4F, M6811_TMSK1, M6811_OC4I },
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{ M6811_INT_OUTCMP5, M6811_TFLG1, M6811_OC5F, M6811_TMSK1, M6811_OC5I },
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/* Input compare interrupts. */
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{ M6811_INT_INCMP1, M6811_TFLG1, M6811_IC1F, M6811_TMSK1, M6811_IC1I },
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{ M6811_INT_INCMP2, M6811_TFLG1, M6811_IC2F, M6811_TMSK1, M6811_IC2I },
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{ M6811_INT_INCMP3, M6811_TFLG1, M6811_IC3F, M6811_TMSK1, M6811_IC3I },
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#if 0
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{ M6811_INT_COPRESET, M6811_CONFIG, M6811_NOCOP, 0, 0 },
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{ M6811_INT_COPFAIL, M6811_CONFIG, M6811_NOCOP, 0, 0 }
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#endif
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};
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#define TableSize(X) (sizeof X / sizeof(X[0]))
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#define CYCLES_MAX ((((signed64) 1) << 62) - 1)
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/* Initialize the interrupts of the processor. */
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int
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interrupts_initialize (struct _sim_cpu *proc)
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{
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struct interrupts *interrupts = &proc->cpu_interrupts;
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int i;
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interrupts->cpu = proc;
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interrupts->pending_mask = 0;
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interrupts->vectors_addr = 0xffc0;
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interrupts->nb_interrupts_raised = 0;
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interrupts->min_mask_cycles = CYCLES_MAX;
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interrupts->max_mask_cycles = 0;
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interrupts->last_mask_cycles = 0;
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interrupts->start_mask_cycle = -1;
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interrupts->xirq_start_mask_cycle = -1;
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interrupts->xirq_max_mask_cycles = 0;
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interrupts->xirq_min_mask_cycles = CYCLES_MAX;
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interrupts->xirq_last_mask_cycles = 0;
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for (i = 0; i < M6811_INT_NUMBER; i++)
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{
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interrupts->interrupt_order[i] = i;
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}
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return 0;
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}
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/* Update the mask of pending interrupts. This operation must be called
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when the state of some 68HC11 IO registers changes. It looks the
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different registers that indicate a pending interrupt (timer, SCI, SPI,
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...) and records the interrupt if it's there and enabled. */
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void
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interrupts_update_pending (struct interrupts *interrupts)
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{
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int i;
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uint8 *ioregs;
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unsigned long clear_mask;
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unsigned long set_mask;
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clear_mask = 0;
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set_mask = 0;
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ioregs = &interrupts->cpu->ios[0];
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for (i = 0; i < TableSize(idefs); i++)
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{
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struct interrupt_def *idef = &idefs[i];
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uint8 data;
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/* Look if the interrupt is enabled. */
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if (idef->enable_paddr)
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{
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data = ioregs[idef->enable_paddr];
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if (!(data & idef->enabled_mask))
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{
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/* Disable it. */
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clear_mask |= (1 << idef->int_number);
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continue;
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}
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}
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/* Interrupt is enabled, see if it's there. */
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data = ioregs[idef->int_paddr];
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if (!(data & idef->int_mask))
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{
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/* Disable it. */
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clear_mask |= (1 << idef->int_number);
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continue;
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}
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/* Ok, raise it. */
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set_mask |= (1 << idef->int_number);
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}
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/* Some interrupts are shared (M6811_INT_SCI) so clear
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the interrupts before setting the new ones. */
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interrupts->pending_mask &= ~clear_mask;
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interrupts->pending_mask |= set_mask;
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}
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/* Finds the current active and non-masked interrupt.
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Returns the interrupt number (index in the vector table) or -1
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if no interrupt can be serviced. */
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int
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interrupts_get_current (struct interrupts *interrupts)
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{
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int i;
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if (interrupts->pending_mask == 0)
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return -1;
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/* SWI and illegal instructions are simulated by an interrupt.
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They are not maskable. */
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if (interrupts->pending_mask & (1 << M6811_INT_SWI))
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{
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interrupts->pending_mask &= ~(1 << M6811_INT_SWI);
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return M6811_INT_SWI;
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}
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if (interrupts->pending_mask & (1 << M6811_INT_ILLEGAL))
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{
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interrupts->pending_mask &= ~(1 << M6811_INT_ILLEGAL);
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return M6811_INT_ILLEGAL;
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}
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/* If there is a non maskable interrupt, go for it (unless we are masked
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by the X-bit. */
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if (interrupts->pending_mask & (1 << M6811_INT_XIRQ))
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{
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if (cpu_get_ccr_X (interrupts->cpu) == 0)
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{
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interrupts->pending_mask &= ~(1 << M6811_INT_XIRQ);
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return M6811_INT_XIRQ;
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}
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return -1;
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}
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/* Interrupts are masked, do nothing. */
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if (cpu_get_ccr_I (interrupts->cpu) == 1)
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{
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return -1;
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}
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/* Returns the first interrupt number which is pending.
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The interrupt priority is specified by the table `interrupt_order'.
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For these interrupts, the pending mask is cleared when the program
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performs some actions on the corresponding device. If the device
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is not reset, the interrupt remains and will be re-raised when
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we return from the interrupt (see 68HC11 pink book). */
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for (i = 0; i < M6811_INT_NUMBER; i++)
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{
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enum M6811_INT int_number = interrupts->interrupt_order[i];
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if (interrupts->pending_mask & (1 << int_number))
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{
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return int_number;
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}
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}
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return -1;
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}
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/* Process the current interrupt if there is one. This operation must
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be called after each instruction to handle the interrupts. If interrupts
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are masked, it does nothing. */
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int
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interrupts_process (struct interrupts *interrupts)
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{
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int id;
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uint8 ccr;
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/* See if interrupts are enabled/disabled and keep track of the
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number of cycles the interrupts are masked. Such information is
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then reported by the info command. */
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ccr = cpu_get_ccr (interrupts->cpu);
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if (ccr & M6811_I_BIT)
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{
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if (interrupts->start_mask_cycle < 0)
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interrupts->start_mask_cycle = cpu_current_cycle (interrupts->cpu);
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}
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else if (interrupts->start_mask_cycle >= 0
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&& (ccr & M6811_I_BIT) == 0)
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{
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signed64 t = cpu_current_cycle (interrupts->cpu);
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t -= interrupts->start_mask_cycle;
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if (t < interrupts->min_mask_cycles)
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interrupts->min_mask_cycles = t;
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if (t > interrupts->max_mask_cycles)
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interrupts->max_mask_cycles = t;
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interrupts->start_mask_cycle = -1;
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interrupts->last_mask_cycles = t;
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}
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if (ccr & M6811_X_BIT)
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{
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if (interrupts->xirq_start_mask_cycle < 0)
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interrupts->xirq_start_mask_cycle
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= cpu_current_cycle (interrupts->cpu);
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}
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else if (interrupts->xirq_start_mask_cycle >= 0
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&& (ccr & M6811_X_BIT) == 0)
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{
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signed64 t = cpu_current_cycle (interrupts->cpu);
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t -= interrupts->xirq_start_mask_cycle;
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if (t < interrupts->xirq_min_mask_cycles)
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interrupts->xirq_min_mask_cycles = t;
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if (t > interrupts->xirq_max_mask_cycles)
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interrupts->xirq_max_mask_cycles = t;
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interrupts->xirq_start_mask_cycle = -1;
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interrupts->xirq_last_mask_cycles = t;
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}
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id = interrupts_get_current (interrupts);
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if (id >= 0)
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{
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uint16 addr;
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cpu_push_all (interrupts->cpu);
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addr = memory_read16 (interrupts->cpu,
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interrupts->vectors_addr + id * 2);
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cpu_call (interrupts->cpu, addr);
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/* Now, protect from nested interrupts. */
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if (id == M6811_INT_XIRQ)
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{
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cpu_set_ccr_X (interrupts->cpu, 1);
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}
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else
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{
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cpu_set_ccr_I (interrupts->cpu, 1);
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}
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interrupts->nb_interrupts_raised++;
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cpu_add_cycles (interrupts->cpu, 14);
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return 1;
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}
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return 0;
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}
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void
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interrupts_raise (struct interrupts *interrupts, enum M6811_INT number)
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{
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interrupts->pending_mask |= (1 << number);
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interrupts->nb_interrupts_raised ++;
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}
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void
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interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
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{
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signed64 t;
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sim_io_printf (sd, "Interrupts Info:\n");
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sim_io_printf (sd, " Interrupts raised: %lu\n",
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interrupts->nb_interrupts_raised);
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if (interrupts->start_mask_cycle >= 0)
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{
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t = cpu_current_cycle (interrupts->cpu);
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t -= interrupts->start_mask_cycle;
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if (t > interrupts->max_mask_cycles)
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interrupts->max_mask_cycles = t;
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sim_io_printf (sd, " Current interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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}
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t = interrupts->min_mask_cycles == CYCLES_MAX ?
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interrupts->max_mask_cycles :
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interrupts->min_mask_cycles;
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sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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t = interrupts->max_mask_cycles;
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sim_io_printf (sd, " Longest interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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t = interrupts->last_mask_cycles;
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sim_io_printf (sd, " Last interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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if (interrupts->xirq_start_mask_cycle >= 0)
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{
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t = cpu_current_cycle (interrupts->cpu);
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t -= interrupts->xirq_start_mask_cycle;
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if (t > interrupts->xirq_max_mask_cycles)
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interrupts->xirq_max_mask_cycles = t;
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sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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}
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t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ?
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interrupts->xirq_max_mask_cycles :
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interrupts->xirq_min_mask_cycles;
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sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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t = interrupts->xirq_max_mask_cycles;
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sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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t = interrupts->xirq_last_mask_cycles;
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sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n",
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cycle_to_string (interrupts->cpu, t));
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}
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