Tsukasa OI c6422d7be7 sim/riscv: fix multiply instructions on simulator ... After this commit: commit 0938b032da Date: Wed Feb 2 10:06:15 2022 +0900 RISC-V: Add 'Zmmul' extension in assembler. some instructions in the RISC-V simulator stopped working as a new instruction class 'INSN_CLASS_ZMMUL' was added, and some existing instructions were moved into this class. The simulator doesn't currently handle this instruction class, and so the instructions will now cause an illegal instruction trap. This commit adds support for INSN_CLASS_ZMMUL, and adds a test that ensures the affected instructions can be executed by the simulator. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Andrew Burgess <aburgess@redhat.com>		2022-10-11 12:38:36 +01:00
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allinsn.exp	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
m-ext.s	sim/riscv: fix multiply instructions on simulator	2022-10-11 12:38:36 +01:00
pass.s
testutils.inc