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binutils-gdb/sim/testsuite/mips/r6-removed.csv
Faraz Shahbazker 06c441ccef sim: mips: Add simulator support for mips32r6/mips64r6 
2022-02-01  Ali Lown  <ali.lown@imgtec.com>
	    Andrew Bennett  <andrew.bennett@imgtec.com>
	    Dragan Mladjenovic  <dragan.mladjenovic@rt-rk.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21,
	EXTEND26): New macros.

sim/mips/ChangeLog:
	* Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen.
	* configure: Regenerate.
	* configure.ac: Support mipsisa32r6 and mipsisa64r6.
	(sim_engine_run): Pick simulator model from processor specified
	in e_flags.
	* cp1.c (value_fpr): Handle fmt_dc32.
	(fp_unary, fp_binary): Zero initialize locals.
	(update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac,
	fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub):
	New functions.
	(sim_fpu_class_mips_mapping): New.
	* cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define.
	* interp.c (MIPSR6_P): New.
	(load_word): Allow unaligned memory access for MIPSR6.
	* micromips.igen (sc, scd): Adapt to new do_sc* helper signature.
	* mips.igen: Add *r6 models.
	(signal_if_cti, forbiddenslot32): New helpers.
	(delayslot32): Use signal_if_cti.
	(do_sc, do_scd); Add store_ll_bit parameter.
	(sc, scd): Adapt to previous change.
	(nal, beq, bal): New definitions for *r6.
	(sll): Split nop and ssnop cases into ...
	(nop, ssnop): New definitions.
	(loadstore_ea): Use the 32-bit compatibility adressing.
	(cache): Split logic into ...
	(do_cache): New helper.
	(check_fpu): Select IEEE 754-2008 mode for R6.
	(not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add,
	li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd,
	daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra,
	dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr,
	jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror,
	rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav,
	srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt,
	tltu, tne, xor, xori, check_fmt_p, do_load_double,
	do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT,
	cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1,
	dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT,
	mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT,
	sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f,
	bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp,
	tlbr, tlbwi, tlbwr): Enable on *r6 models.
	* mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu,
	dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr,
	wsbh): Likewise.
	* mips3264r6.igen: New file.
	* sim-main.h (FP_formats): Add fmt_dc32.
	(FORBIDDEN_SLOT): New macros.
	(simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines.
	(fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina,
	fp_maxa, fp_fmadd, fp_fmsub): New declarations.
	(R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA,
	MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping
	previous declarations.

sim/testsuite/mips/ChangeLog:
	* basic.exp: Add r6-*.s tests.
	(run_r6_removed_test): New function.
	(run_endian_tests): New function.
	* hilo-hazard-3.s: Skip for mips*r6.
	* r2-fpu.s: New test.
	* r6-64.s: New test.
	* r6-branch.s: New test.
	* r6-forbidden.s: New test.
	* r6-fpu.s: New test.
	* r6-llsc-dp.s: New test.
	* r6-llsc-wp.s: New test.
	* r6-removed.csv: New test.
	* r6-removed.s: New test.
	* r6.s: New test.
	* utils-r6.inc: New inc.
2022-02-04 19:37:26 -05:00

1.1 KiB
Raw Blame History

1BC1F0x45000000
2BEQL0x50000000
3BGEZAL0x04310000
4BGEZALL0x04130000
5BGEZL0x04030000
6BLTZALL0x04120000
7BLTZL0x04020000
8BNEL0x54000000
9C.DEQ.D0x44000030
10CACHE0xbc000000
11CVT.PS.S0x46000026
12CVT.S.PL0x46c00028
13CVT.S.PU0x46c00020
14DCLO0x70000025
15DCLZ0x70000024
16LDL0x68000000
17LDR0x6c000000
18LDXC10x4c000001
19LL0xc0000000
20LLD0xd0000000
21LUXC10x4c000005
22LWL0x88000000
23LWLE0x7c000019
24LWR0x98000000
25LWRE0x7c00001a
26LWXC10x4c000000
27MADD0x70000000
28MADD.D0x4c000020
29MADDU0x70000001
30MOVF0x00000001
31MOVF.D0x44000011
32MOVN.D0x44000013
33MOVT0x00010001
34MOVT.D0x44010011
35MOVZ.D0x44000012
36MSUB0x70000004
37MSUB.D0x4c000028
38MSUBU0x70000005
39MUL0x70000002
40NEG.S0x44000007
41NMADD.D0x4c000030
42NMSUB.D0x4c000038
43PLL.PS0x46c0002c
44PLU.PS0x46c0002d
45PREF0xcc000000
46PREFX0x4c00000f
47PUL.PS0x46c0005e
48PUU.PS0x46c0002f
49RINT.fmt0x4400001a
50SC0xe0000000
51SCD0xf0000000
52SDBBP0x7000003f
53SDL0xb0000000
54SDR0xb4000000
55SDXC10x4c000009
56SUB.D0x44000001
57SUXC10x4c00000d
58SWL0xa8000000
59SWLE0x7c000021
60SWR0xb8000000
61SWRE0x7c000022
62SWXC10x4c000008
63TEQI0x040c0000
64TGEI0x04080000
65TGEIU0x04090000
66TLTI0x040a0000
67TLTIU0x040b0000
68TNEI0x040c0000