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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
74 lines
2.0 KiB
Plaintext
74 lines
2.0 KiB
Plaintext
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
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# mach: fr500 frv
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.include "testutils.inc"
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start
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.global align
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align:
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x100,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_addr ok1,lr
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set_psr_et 1
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set_gr_immed 0xdeadbeef,gr17
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set_gr_immed 0,gr15
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inc_gr_immed 2,sp ; out of alignment
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test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked
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sti gr17,@(sp,0) ; no exception
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ldi @(sp,-2),gr18 ; stored at aligned address
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test_gr_immed 0xdeadbeef,gr18
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ldi @(sp,0),gr19 ; no exception
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test_gr_immed 0xdeadbeef,gr19
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and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
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set_gr_addr bad1,gr16
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bad1: sti gr17,@(sp,0) ; misaligned write in slot I1
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test_gr_immed 1,gr15
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set_gr_addr bad3,gr16
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set_gr_gr sp,gr20
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set_gr_immed 1,gr21
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set_gr_immed 0x10101010,gr10
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bad2: nop.p
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bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2
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test_gr_immed 2,gr15 ; handler was called
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test_gr_immed 0x10101010,gr10 ; gr10 not updated
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test_gr_immed 1,gr21 ; gr21 not updated
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inc_gr_immed 1,gr20
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test_gr_gr gr20,sp ; sp updated
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pass
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; exception handler
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ok1:
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cmpi gr15,0,icc0
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bne icc0,0,load
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; handle interrupt on store
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test_spr_immed 0x100,esfr1 ; esr8 is active
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test_spr_gr epcr8,gr16
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test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid
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test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set
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test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set
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test_spr_gr ear8,sp
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test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set
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test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3
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test_spr_gr edr3,gr17 ; edr3 is set
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bra ret
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load:
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; handle interrupt on load
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test_spr_immed 0x200,esfr1 ; esr9 is active
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test_spr_gr epcr9,gr16
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test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid
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test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set
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test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set
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test_spr_gr ear9,sp
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test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set
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ret:
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inc_gr_immed 1,gr15
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rett 0
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fail
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