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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
360 lines
9.6 KiB
Plaintext
360 lines
9.6 KiB
Plaintext
# frv testcase for smass $GRi,$GRj
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# mach: fr405 fr450
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.include "../testutils.inc"
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start
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.global smass
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smass1:
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; Positive operands
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 3,gr7
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test_gr_immed 2,gr8
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test_spr_immed 7,iacc0l ; result 3*2+1
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test_spr_immed 0,iacc0h
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smass2:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 1,gr7
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test_gr_immed 2,gr8
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test_spr_immed 3,iacc0l ; result 1*2+1
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test_spr_immed 0,iacc0h
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smass3:
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set_gr_immed 2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed 2,gr7
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test_spr_immed 3,iacc0l ; result 2*1+1
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test_spr_immed 0,iacc0h
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smass4:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 0,gr7
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test_spr_immed 1,iacc0l ; result 0*2+1
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test_spr_immed 0,iacc0h
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smass5:
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set_gr_immed 2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed 2,gr7
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test_spr_immed 1,iacc0l ; result 2*0+1
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test_spr_immed 0,iacc0h
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smass6:
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set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x3fff,0xffff,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1
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test_spr_immed 0,iacc0h
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smass7:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1
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test_spr_immed 0,iacc0h
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smass8:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed 4,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_immed 1,iacc0l ; 40000000*4+1
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test_spr_immed 1,iacc0h
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smass9:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1
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test_spr_limmed 0x3fff,0xffff,iacc0h
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smass10:
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; Mixed operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed -3,gr7
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test_spr_immed -5,iacc0l ; -3*2+1
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test_spr_immed -1,iacc0h
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smass11:
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 3,gr7
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test_spr_immed -5,iacc0l ; 3*-2+1
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test_spr_immed -1,iacc0h
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smass12:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 1,gr7
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test_spr_immed -1,iacc0l ; 1*-2+1
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test_spr_immed -1,iacc0h
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smass13:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed -2,gr7
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test_spr_immed -1,iacc0l ; -2*1+1
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test_spr_immed -1,iacc0h
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smass14:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 0,gr7
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test_spr_immed 1,iacc0l ; 0*-2+1
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test_spr_immed 0,iacc0h
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smass15:
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set_gr_immed -2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed -2,gr7
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test_spr_immed 1,iacc0l ; -2*0+1
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test_spr_immed 0,iacc0h
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smass16:
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set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x2000,0x0001,gr7
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test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1
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test_spr_limmed 0xffff,0xffff,iacc0h
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smass17:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1
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test_spr_limmed 0xffff,0xffff,iacc0h
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smass18:
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set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0001,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1
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test_spr_limmed 0xffff,0xffff,iacc0h
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smass19:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed -4,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1
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test_spr_limmed 0xffff,0xffff,iacc0h
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smass20:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1
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test_spr_limmed 0xc000,0x0000,iacc0h
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smass21:
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; Negative operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -3,gr7
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test_spr_immed 7,iacc0l ; -3*-2+1
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test_spr_immed 0,iacc0h
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smass22:
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set_gr_immed -1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -1,gr7
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test_spr_immed 3,iacc0l ; -1*-2+1
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test_spr_immed 0,iacc0h
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smass23:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed -1,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -1,gr8
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test_gr_immed -2,gr7
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test_spr_immed 3,iacc0l ; -2*-1+1
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test_spr_immed 0,iacc0h
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smass24:
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set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0xc000,0x0001,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1
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test_spr_immed 0,iacc0h
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smass25:
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set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0xc000,0x0000,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1
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test_spr_immed 0,iacc0h
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smass26:
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set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
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set_gr_immed -4,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_immed -4,gr8
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test_gr_limmed 0xc000,0x0000,gr7
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test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1
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test_spr_immed 1,iacc0h
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smass27:
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set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
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set_gr_limmed 0x8000,0x0001,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0001,gr8
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test_gr_limmed 0x8000,0x0001,gr7
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test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1
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test_spr_limmed 0x3fff,0xffff,iacc0h
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smass28:
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set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x8000,0x0000,gr7
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test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1
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test_spr_limmed 0x4000,0x0000,iacc0h
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smass29:
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set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0xffff,0xfffe,iacc0l
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set_spr_limmed 0x4000,0x0000,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe
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smass30:
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set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0xffff,0xffff,iacc0l
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set_spr_limmed 0x4000,0x0000,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff
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smass31:
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set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0xffff,0xffff,iacc0l
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set_spr_limmed 0x7fff,0xffff,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff
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smass32:
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set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0x8000,0x0000,iacc0l
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set_spr_limmed 0xbfff,0xffff,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000
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smass33:
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set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0x7fff,0xffff,iacc0l
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set_spr_limmed 0xbfff,0xffff,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
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smass34:
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set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0x0000,0x0000,iacc0l
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set_spr_limmed 0x8000,0x0000,iacc0h
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smass gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000
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pass
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