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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
315 lines
6.0 KiB
ArmAsm
315 lines
6.0 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
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// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
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// Supervisor mode
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(std.inc)
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include(mmrs.inc)
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include(selfcheck.inc)
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#ifndef ITABLE
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#define ITABLE 0xF0000000
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x20
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#endif
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// This test embeds .text offsets, so pad our test so it lines up.
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.space 0x64
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// Boot code
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BOOT :
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INIT_R_REGS(0); // Initialize Dregs
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INIT_P_REGS(0); // Initialize Pregs
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CHECK_INIT(p5, 0x00BFFFFC);
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R0 = -1; // Change this to mask interrupts (*)
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[ P0 ] = R0; // IMASK
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LD32_LABEL(p1, START);
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LD32(p0, EVT15);
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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LD32_LABEL(r7, DUMMY);
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RETI = r7;
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RAISE 15; // after we RTI, INT 15 should be taken
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NOP; // Workaround for Bug 217
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RTI;
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NOP;
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NOP;
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NOP;
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DUMMY:
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NOP;
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NOP;
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NOP;
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NOP;
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// .code 0x200
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START:
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WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer
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WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
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// TBUFPWR = 1
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// TBUFEN = 1
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// TBUFOVF = 0
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// CMPLP = 0
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NOP;
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NOP;
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NOP;
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NOP;
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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RTI;
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STARTUSER:
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LD32_LABEL(sp, USTACK); // setup the stack pointer
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FP = SP; // set frame pointer
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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NOP;
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NOP;
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NOP;
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JUMP.S label1;
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R4.L = 0x1111;
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R4.H = 0x1111;
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NOP;
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NOP;
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NOP;
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label2: R5.H = 0x7777;
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R5.L = 0x7888;
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JUMP.S label3;
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R6.L = 0x1111;
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R6.H = 0x1111;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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label1: R4.H = 0x5555;
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R4.L = 0x6666;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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JUMP.S label2;
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R5.L = 0x1111;
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R5.H = 0x1111;
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NOP;
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NOP;
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NOP;
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NOP;
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label3:
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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// Checks the contents of the Trace Buffer
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EXCPT 0;
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NOP; NOP; NOP; NOP;
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CHECKREG(r2, 0x00000006);
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CHECKREG(r1, 0x00000416);
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CHECKREG(r0, 0x000002aa);
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CHECKREG(r3, 0x0000029a);
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CHECKREG(r4, 0x00000262);
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CHECKREG(r5, 0x00000004);
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CHECKREG(r6, 0x0000025a);
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CHECKREG(r7, 0x00000288);
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NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP;
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EXCPT 1;
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NOP; NOP; NOP; NOP;
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CHECKREG(r2, 0x00000005);
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CHECKREG(r1, 0x00000416);
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CHECKREG(r0, 0x00000304);
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CHECKREG(r3, 0x000002ac);
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CHECKREG(r4, 0x00000470);
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CHECKREG(r5, 0x00000003);
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CHECKREG(r6, 0x00000276);
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CHECKREG(r7, 0x0000024a);
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NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP;
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EXCPT 2;
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NOP; NOP; NOP; NOP;
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CHECKREG(r2, 0x00000004);
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CHECKREG(r1, 0x00000416);
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CHECKREG(r0, 0x0000035e);
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CHECKREG(r3, 0x00000306);
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CHECKREG(r4, 0x00000470);
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CHECKREG(r5, 0x00000002);
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CHECKREG(r6, 0x00000244);
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CHECKREG(r7, 0x00000242);
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NOP; NOP; NOP; NOP;
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EXCPT 3;
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NOP; NOP; NOP; NOP;
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CHECKREG(r2, 0x00000003);
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CHECKREG(r1, 0x00000416);
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CHECKREG(r0, 0x000003b0);
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CHECKREG(r3, 0x00000360);
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CHECKREG(r4, 0x00000470);
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CHECKREG(r5, 0x00000001);
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CHECKREG(r6, 0x00000238);
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CHECKREG(r7, 0x00000236);
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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dbg_pass; // Call Endtest Macro
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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RTN;
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XHANDLE: // Exception Handler 3
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R7 = SEQSTAT;
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RD_MMR(TBUFSTAT, p0, r2);
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RD_MMR(TBUF, p0, r1);
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RD_MMR(TBUF, p0, r0);
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RD_MMR(TBUF, p0, r3);
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RD_MMR(TBUF, p0, r4);
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RD_MMR(TBUFSTAT, p0, r5);
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RD_MMR(TBUF, p0, r6);
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RD_MMR(TBUF, p0, r7);
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NOP; NOP; NOP; NOP;
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RTX;
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NOP; NOP; NOP; NOP;
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NOP; NOP; NOP; NOP;
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HWHANDLE: // HW Error Handler 5
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RTI;
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THANDLE: // Timer Handler 6
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RTI;
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I7HANDLE: // IVG 7 Handler
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RTI;
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I8HANDLE: // IVG 8 Handler
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RTI;
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I9HANDLE: // IVG 9 Handler
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RTI;
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I10HANDLE: // IVG 10 Handler
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RTI;
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I11HANDLE: // IVG 11 Handler
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RTI;
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I12HANDLE: // IVG 12 Handler
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RTI;
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I13HANDLE: // IVG 13 Handler
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RTI;
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I14HANDLE: // IVG 14 Handler
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RTI;
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I15HANDLE: // IVG 15 Handler
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RTI;
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.space (STACKSIZE);
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KSTACK:
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.space (STACKSIZE);
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USTACK:
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