mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
225 lines
4.2 KiB
ArmAsm
225 lines
4.2 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp
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// Spec Reference: interrupt loopsetup_ldst
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# mach: bfin
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#include "test.h"
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.include "testutils.inc"
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start
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A0 = 0; // reset accumulators
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A1 = 0;
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P1 = 3;
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P2 = 4;
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LD32(r0, 0x00200005);
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LD32(r1, 0x00300010);
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LD32(r2, 0x00500012);
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LD32(r3, 0x00600024);
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LD32(r4, 0x00700016);
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LD32(r5, 0x00900028);
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LD32(r6, 0x0a000030);
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LD32(r7, 0x00b00044);
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loadsym I0, DATA0;
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loadsym I1, DATA1;
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R0 = [ I0 ++ ];
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R1 = [ I1 ++ ];
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LSETUP ( start1 , end1 ) LC0 = P1;
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start1: R0 += 1;
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R1 += 2;
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A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; // dsp32mac dual
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// a1 += h*h, a0 += l*l (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac
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R2 = ( R2 + R5 ) << 1; // alu2op
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DIVQ ( R5 , R3 );
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R1 <<= R5;
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R1 >>>= R1;
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R6 = ~ R0;
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//MY_GEN_INT(10, 1)
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DIVQ ( R5 , R2 );
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R0 = R3.B (X);
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DIVS ( R7 , R0 );
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end1: R2 += 3;
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R3 = ( A0 += A1 );
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CHECKREG(r0, 0x00000024);
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CHECKREG(r1, 0x00000000);
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CHECKREG(r2, 0x0670098D);
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CHECKREG(r3, 0x000015EC);
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CHECKREG(r4, 0x00700016);
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CHECKREG(r5, 0x0B240A39);
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CHECKREG(r6, 0xFFF2FFFC);
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CHECKREG(r7, 0x05800220);
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A0 = 0;
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A1 = 0;
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LSETUP ( start2 , end2 ) LC0 = P2;
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start2: R4 += 4;
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//a1 += h*h, a0 += l*l (r0,r1), r0 = [i0--], r1 = [i1--];
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A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ];
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R1 <<= R5;
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R6 = R7.B (Z);
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R2 = - R6;
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R3 = R4.L (Z);
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DIVS ( R1 , R1 );
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R6 = - R0;
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R0 >>= R0;
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DIVS ( R4 , R7 );
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//MY_GEN_INT(13, 1)
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R1 = R2.L (Z);
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end2: R5 += -5;
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R6 = ( A0 += A1 );
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CHECKREG(r0, 0x00000000);
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CHECKREG(r1, 0x0000FFE0);
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CHECKREG(r2, 0xFFFFFFE0);
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CHECKREG(r3, 0x000000EC);
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CHECKREG(r4, 0x070001D8);
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CHECKREG(r5, 0x0B240A25);
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CHECKREG(r6, 0x00000000);
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CHECKREG(r7, 0x05800220);
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LD32(r0, 0x01200805);
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LD32(r1, 0x02300710);
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LD32(r2, 0x03500612);
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LD32(r3, 0x04600524);
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LD32(r4, 0x05700416);
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LD32(r5, 0x06900328);
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LD32(r6, 0x0a700230);
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LD32(r7, 0x08b00044);
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loadsym I2, DATA0;
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loadsym I3, DATA1;
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[ I2 ++ ] = R0;
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[ I3 ++ ] = R1;
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LSETUP ( start3 , end3 ) LC0 = P1;
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start3:
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[ I2 ++ ] = R2;
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[ I3 ++ ] = R3;
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R2 += 1;
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end3:
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R3 += 1;
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A0 = 0;
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A1 = 0;
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LSETUP ( start4 , end4 ) LC0 = P2;
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R0 = [ I0 -- ];
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R1 = [ I1 -- ];
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start4:
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// a1 += h*h, a0 += l*l (r0,r1), r0 = [i2--], r1 = [i3--];
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A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ];
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R4 = R4 + R0; // comp3op
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R5 = R7.L (Z);
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R4 >>>= R5;
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R0 = R7.B (X);
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DIVQ ( R6 , R6 );
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//MY_GEN_INT(7, 1)
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end4: R5 = R5 + R1;
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R6 = ( A0 += A1 );
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R7 = ( A0 += A1 );
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CHECKREG(r0, 0x00000044);
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CHECKREG(r1, 0x04600524);
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CHECKREG(r2, 0x03500615);
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CHECKREG(r3, 0x04600527);
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CHECKREG(r4, 0x00000000);
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CHECKREG(r5, 0x04600568);
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CHECKREG(r6, 0x007C3498);
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CHECKREG(r7, 0x00812098);
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pass; // End the test
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//
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// Data Segment
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//
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.data
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DATA0:
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.dd 0x000a0000
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.dd 0x000b0001
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.dd 0x000c0002
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.dd 0x000d0003
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.dd 0x000e0004
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.dd 0x000f0005
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.dd 0x00100006
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.dd 0x00200007
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.dd 0x00300008
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.dd 0x00400009
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.dd 0x0050000a
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.dd 0x0060000b
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.dd 0x0070000c
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.dd 0x0080000d
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.dd 0x0090000e
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.dd 0x0100000f
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.dd 0x02000010
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.dd 0x03000011
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.dd 0x04000012
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.dd 0x05000013
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.dd 0x06000014
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.dd 0x001a0000
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.dd 0x001b0001
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.dd 0x001c0002
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.dd 0x001d0003
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.dd 0x00010004
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.dd 0x00010005
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.dd 0x02100006
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.dd 0x02200007
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.dd 0x02300008
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.dd 0x02200009
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.dd 0x0250000a
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.dd 0x0260000b
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.dd 0x0270000c
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.dd 0x0280000d
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.dd 0x0290000e
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.dd 0x2100000f
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.dd 0x22000010
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.dd 0x22000011
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.dd 0x24000012
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.dd 0x25000013
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.dd 0x26000014
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DATA1:
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.dd 0x00f00100
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.dd 0x00e00101
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.dd 0x00d00102
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.dd 0x00c00103
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.dd 0x00b00104
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.dd 0x00a00105
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.dd 0x00900106
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.dd 0x00800107
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.dd 0x00100108
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.dd 0x00200109
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.dd 0x0030010a
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.dd 0x0040010b
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.dd 0x0050011c
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.dd 0x0060010d
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.dd 0x0070010e
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.dd 0x0080010f
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.dd 0x00900110
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.dd 0x01000111
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.dd 0x02000112
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.dd 0x03000113
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.dd 0x04000114
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.dd 0x05000115
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.dd 0x03f00100
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.dd 0x03e00101
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.dd 0x03d00102
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.dd 0x03c00103
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.dd 0x03b00104
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.dd 0x03a00105
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.dd 0x03900106
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.dd 0x03800107
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.dd 0x03100108
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.dd 0x03200109
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.dd 0x0330010a
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.dd 0x0330010b
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.dd 0x0350011c
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.dd 0x0360010d
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.dd 0x0370010e
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.dd 0x0380010f
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.dd 0x03900110
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.dd 0x31000111
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.dd 0x32000112
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.dd 0x33000113
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.dd 0x34000114
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