Jaydeep Patil 1c37b30945 sim/riscv: fix JALR instruction simulation ... Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>		2023-10-18 17:55:31 +01:00
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acinclude.m4
ChangeLog-2021
interp.c
local.mk
machs.c
machs.h
model_list.def
riscv-sim.h
sim-main.c
sim-main.h