mirror of
https://sourceware.org/git/binutils-gdb.git
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bb651e8b7f
gas/ * config/tc-i386.c (cpu_arch): Add .TSXLDTRK. (cpu_noarch): Likewise. * doc/c-i386.texi: Document TSXLDTRK. * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests. * testsuite/gas/i386/tsxldtrk.d: Likewise. * testsuite/gas/i386/tsxldtrk.s: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, (prefix_table): New instructions (see prefixes above). (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, CPU_ANY_TSXLDTRK_FLAGS. (cpu_flags): Add CpuTSXLDTRK. * i386-opc.h (enum): Add CpuTSXLDTRK. (i386_cpu_flags): Add cputsxldtrk. * i386-opc.tbl: Add XSUSPLDTRK insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
947 lines
26 KiB
C
947 lines
26 KiB
C
/* Declarations for Intel 80386 opcode table
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Copyright (C) 2007-2020 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "opcode/i386.h"
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#ifdef HAVE_LIMITS_H
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#include <limits.h>
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#endif
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#ifndef CHAR_BIT
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#define CHAR_BIT 8
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#endif
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/* Position of cpu flags bitfiled. */
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enum
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{
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/* i186 or better required */
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Cpu186 = 0,
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/* i286 or better required */
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Cpu286,
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/* i386 or better required */
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Cpu386,
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/* i486 or better required */
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Cpu486,
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/* i585 or better required */
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Cpu586,
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/* i686 or better required */
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Cpu686,
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/* CMOV Instruction support required */
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CpuCMOV,
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/* FXSR Instruction support required */
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CpuFXSR,
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/* CLFLUSH Instruction support required */
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CpuClflush,
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/* NOP Instruction support required */
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CpuNop,
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/* SYSCALL Instructions support required */
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CpuSYSCALL,
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/* Floating point support required */
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Cpu8087,
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/* i287 support required */
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Cpu287,
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/* i387 support required */
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Cpu387,
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/* i686 and floating point support required */
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Cpu687,
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/* SSE3 and floating point support required */
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CpuFISTTP,
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/* MMX support required */
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CpuMMX,
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/* SSE support required */
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CpuSSE,
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/* SSE2 support required */
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CpuSSE2,
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/* 3dnow! support required */
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Cpu3dnow,
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/* 3dnow! Extensions support required */
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Cpu3dnowA,
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/* SSE3 support required */
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CpuSSE3,
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/* VIA PadLock required */
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CpuPadLock,
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/* AMD Secure Virtual Machine Ext-s required */
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CpuSVME,
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/* VMX Instructions required */
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CpuVMX,
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/* SMX Instructions required */
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CpuSMX,
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/* SSSE3 support required */
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CpuSSSE3,
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/* SSE4a support required */
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CpuSSE4a,
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/* LZCNT support required */
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CpuLZCNT,
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/* POPCNT support required */
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CpuPOPCNT,
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/* SSE4.1 support required */
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CpuSSE4_1,
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/* SSE4.2 support required */
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CpuSSE4_2,
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/* AVX support required */
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CpuAVX,
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/* AVX2 support required */
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CpuAVX2,
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/* Intel AVX-512 Foundation Instructions support required */
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CpuAVX512F,
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/* Intel AVX-512 Conflict Detection Instructions support required */
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CpuAVX512CD,
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/* Intel AVX-512 Exponential and Reciprocal Instructions support
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required */
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CpuAVX512ER,
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/* Intel AVX-512 Prefetch Instructions support required */
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CpuAVX512PF,
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/* Intel AVX-512 VL Instructions support required. */
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CpuAVX512VL,
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/* Intel AVX-512 DQ Instructions support required. */
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CpuAVX512DQ,
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/* Intel AVX-512 BW Instructions support required. */
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CpuAVX512BW,
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/* Intel L1OM support required */
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CpuL1OM,
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/* Intel K1OM support required */
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CpuK1OM,
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/* Intel IAMCU support required */
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CpuIAMCU,
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/* Xsave/xrstor New Instructions support required */
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CpuXsave,
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/* Xsaveopt New Instructions support required */
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CpuXsaveopt,
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/* AES support required */
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CpuAES,
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/* PCLMUL support required */
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CpuPCLMUL,
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/* FMA support required */
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CpuFMA,
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/* FMA4 support required */
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CpuFMA4,
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/* XOP support required */
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CpuXOP,
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/* LWP support required */
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CpuLWP,
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/* BMI support required */
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CpuBMI,
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/* TBM support required */
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CpuTBM,
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/* MOVBE Instruction support required */
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CpuMovbe,
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/* CMPXCHG16B instruction support required. */
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CpuCX16,
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/* EPT Instructions required */
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CpuEPT,
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/* RDTSCP Instruction support required */
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CpuRdtscp,
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/* FSGSBASE Instructions required */
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CpuFSGSBase,
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/* RDRND Instructions required */
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CpuRdRnd,
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/* F16C Instructions required */
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CpuF16C,
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/* Intel BMI2 support required */
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CpuBMI2,
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/* HLE support required */
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CpuHLE,
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/* RTM support required */
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CpuRTM,
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/* INVPCID Instructions required */
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CpuINVPCID,
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/* VMFUNC Instruction required */
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CpuVMFUNC,
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/* Intel MPX Instructions required */
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CpuMPX,
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/* 64bit support available, used by -march= in assembler. */
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CpuLM,
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/* RDRSEED instruction required. */
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CpuRDSEED,
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/* Multi-presisionn add-carry instructions are required. */
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CpuADX,
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/* Supports prefetchw and prefetch instructions. */
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CpuPRFCHW,
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/* SMAP instructions required. */
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CpuSMAP,
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/* SHA instructions required. */
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CpuSHA,
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/* CLFLUSHOPT instruction required */
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CpuClflushOpt,
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/* XSAVES/XRSTORS instruction required */
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CpuXSAVES,
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/* XSAVEC instruction required */
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CpuXSAVEC,
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/* PREFETCHWT1 instruction required */
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CpuPREFETCHWT1,
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/* SE1 instruction required */
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CpuSE1,
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/* CLWB instruction required */
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CpuCLWB,
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/* Intel AVX-512 IFMA Instructions support required. */
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CpuAVX512IFMA,
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/* Intel AVX-512 VBMI Instructions support required. */
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CpuAVX512VBMI,
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/* Intel AVX-512 4FMAPS Instructions support required. */
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CpuAVX512_4FMAPS,
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/* Intel AVX-512 4VNNIW Instructions support required. */
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CpuAVX512_4VNNIW,
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/* Intel AVX-512 VPOPCNTDQ Instructions support required. */
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CpuAVX512_VPOPCNTDQ,
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/* Intel AVX-512 VBMI2 Instructions support required. */
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CpuAVX512_VBMI2,
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/* Intel AVX-512 VNNI Instructions support required. */
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CpuAVX512_VNNI,
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/* Intel AVX-512 BITALG Instructions support required. */
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CpuAVX512_BITALG,
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/* Intel AVX-512 BF16 Instructions support required. */
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CpuAVX512_BF16,
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/* Intel AVX-512 VP2INTERSECT Instructions support required. */
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CpuAVX512_VP2INTERSECT,
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/* mwaitx instruction required */
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CpuMWAITX,
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/* Clzero instruction required */
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CpuCLZERO,
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/* OSPKE instruction required */
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CpuOSPKE,
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/* RDPID instruction required */
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CpuRDPID,
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/* PTWRITE instruction required */
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CpuPTWRITE,
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/* CET instructions support required */
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CpuIBT,
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CpuSHSTK,
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/* GFNI instructions required */
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CpuGFNI,
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/* VAES instructions required */
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CpuVAES,
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/* VPCLMULQDQ instructions required */
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CpuVPCLMULQDQ,
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/* WBNOINVD instructions required */
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CpuWBNOINVD,
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/* PCONFIG instructions required */
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CpuPCONFIG,
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/* WAITPKG instructions required */
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CpuWAITPKG,
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/* CLDEMOTE instruction required */
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CpuCLDEMOTE,
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/* MOVDIRI instruction support required */
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CpuMOVDIRI,
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/* MOVDIRR64B instruction required */
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CpuMOVDIR64B,
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/* ENQCMD instruction required */
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CpuENQCMD,
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/* SERIALIZE instruction required */
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CpuSERIALIZE,
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/* RDPRU instruction required */
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CpuRDPRU,
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/* MCOMMIT instruction required */
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CpuMCOMMIT,
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/* SEV-ES instruction(s) required */
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CpuSEV_ES,
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/* TSXLDTRK instruction required */
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CpuTSXLDTRK,
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/* 64bit support required */
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Cpu64,
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/* Not supported in the 64bit mode */
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CpuNo64,
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/* The last bitfield in i386_cpu_flags. */
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CpuMax = CpuNo64
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};
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#define CpuNumOfUints \
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(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
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#define CpuNumOfBits \
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(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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/* If you get a compiler error for zero width of the unused field,
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comment it out. */
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#define CpuUnused (CpuMax + 1)
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/* We can check if an instruction is available with array instead
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of bitfield. */
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typedef union i386_cpu_flags
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{
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struct
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{
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unsigned int cpui186:1;
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unsigned int cpui286:1;
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unsigned int cpui386:1;
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unsigned int cpui486:1;
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unsigned int cpui586:1;
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unsigned int cpui686:1;
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unsigned int cpucmov:1;
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unsigned int cpufxsr:1;
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unsigned int cpuclflush:1;
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unsigned int cpunop:1;
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unsigned int cpusyscall:1;
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unsigned int cpu8087:1;
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unsigned int cpu287:1;
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unsigned int cpu387:1;
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unsigned int cpu687:1;
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unsigned int cpufisttp:1;
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unsigned int cpummx:1;
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unsigned int cpusse:1;
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unsigned int cpusse2:1;
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unsigned int cpua3dnow:1;
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unsigned int cpua3dnowa:1;
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unsigned int cpusse3:1;
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unsigned int cpupadlock:1;
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unsigned int cpusvme:1;
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unsigned int cpuvmx:1;
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unsigned int cpusmx:1;
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unsigned int cpussse3:1;
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unsigned int cpusse4a:1;
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unsigned int cpulzcnt:1;
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unsigned int cpupopcnt:1;
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unsigned int cpusse4_1:1;
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unsigned int cpusse4_2:1;
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unsigned int cpuavx:1;
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unsigned int cpuavx2:1;
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unsigned int cpuavx512f:1;
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unsigned int cpuavx512cd:1;
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unsigned int cpuavx512er:1;
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unsigned int cpuavx512pf:1;
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unsigned int cpuavx512vl:1;
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unsigned int cpuavx512dq:1;
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unsigned int cpuavx512bw:1;
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unsigned int cpul1om:1;
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unsigned int cpuk1om:1;
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unsigned int cpuiamcu:1;
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unsigned int cpuxsave:1;
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unsigned int cpuxsaveopt:1;
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unsigned int cpuaes:1;
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unsigned int cpupclmul:1;
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unsigned int cpufma:1;
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unsigned int cpufma4:1;
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unsigned int cpuxop:1;
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unsigned int cpulwp:1;
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unsigned int cpubmi:1;
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unsigned int cputbm:1;
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unsigned int cpumovbe:1;
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unsigned int cpucx16:1;
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unsigned int cpuept:1;
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unsigned int cpurdtscp:1;
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unsigned int cpufsgsbase:1;
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unsigned int cpurdrnd:1;
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unsigned int cpuf16c:1;
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unsigned int cpubmi2:1;
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unsigned int cpuhle:1;
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unsigned int cpurtm:1;
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unsigned int cpuinvpcid:1;
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unsigned int cpuvmfunc:1;
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unsigned int cpumpx:1;
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unsigned int cpulm:1;
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unsigned int cpurdseed:1;
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unsigned int cpuadx:1;
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unsigned int cpuprfchw:1;
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unsigned int cpusmap:1;
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unsigned int cpusha:1;
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unsigned int cpuclflushopt:1;
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unsigned int cpuxsaves:1;
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unsigned int cpuxsavec:1;
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unsigned int cpuprefetchwt1:1;
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unsigned int cpuse1:1;
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unsigned int cpuclwb:1;
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unsigned int cpuavx512ifma:1;
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unsigned int cpuavx512vbmi:1;
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unsigned int cpuavx512_4fmaps:1;
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unsigned int cpuavx512_4vnniw:1;
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unsigned int cpuavx512_vpopcntdq:1;
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unsigned int cpuavx512_vbmi2:1;
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unsigned int cpuavx512_vnni:1;
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unsigned int cpuavx512_bitalg:1;
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unsigned int cpuavx512_bf16:1;
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unsigned int cpuavx512_vp2intersect:1;
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unsigned int cpumwaitx:1;
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unsigned int cpuclzero:1;
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unsigned int cpuospke:1;
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unsigned int cpurdpid:1;
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unsigned int cpuptwrite:1;
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unsigned int cpuibt:1;
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unsigned int cpushstk:1;
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unsigned int cpugfni:1;
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unsigned int cpuvaes:1;
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unsigned int cpuvpclmulqdq:1;
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unsigned int cpuwbnoinvd:1;
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unsigned int cpupconfig:1;
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unsigned int cpuwaitpkg:1;
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unsigned int cpucldemote:1;
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unsigned int cpumovdiri:1;
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unsigned int cpumovdir64b:1;
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unsigned int cpuenqcmd:1;
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unsigned int cpuserialize:1;
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unsigned int cpurdpru:1;
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unsigned int cpumcommit:1;
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unsigned int cpusev_es:1;
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unsigned int cputsxldtrk:1;
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unsigned int cpu64:1;
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unsigned int cpuno64:1;
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#ifdef CpuUnused
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unsigned int unused:(CpuNumOfBits - CpuUnused);
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#endif
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} bitfield;
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unsigned int array[CpuNumOfUints];
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} i386_cpu_flags;
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/* Position of opcode_modifier bits. */
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enum
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{
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/* has direction bit. */
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D = 0,
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/* set if operands can be both bytes and words/dwords/qwords, encoded the
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canonical way; the base_opcode field should hold the encoding for byte
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operands */
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W,
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/* load form instruction. Must be placed before store form. */
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Load,
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/* insn has a modrm byte. */
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Modrm,
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/* special case for jump insns; value has to be 1 */
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#define JUMP 1
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/* call and jump */
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#define JUMP_DWORD 2
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/* loop and jecxz */
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#define JUMP_BYTE 3
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/* special case for intersegment leaps/calls */
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#define JUMP_INTERSEGMENT 4
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/* absolute address for jump */
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#define JUMP_ABSOLUTE 5
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Jump,
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/* FP insn memory format bit, sized by 0x4 */
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FloatMF,
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/* src/dest swap for floats. */
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FloatR,
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/* needs size prefix if in 32-bit mode */
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#define SIZE16 1
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/* needs size prefix if in 16-bit mode */
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#define SIZE32 2
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/* needs size prefix if in 64-bit mode */
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#define SIZE64 3
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Size,
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/* check register size. */
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CheckRegSize,
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/* instruction ignores operand size prefix and in Intel mode ignores
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mnemonic size suffix check. */
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#define IGNORESIZE 1
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/* default insn size depends on mode */
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#define DEFAULTSIZE 2
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MnemonicSize,
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/* any memory size */
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Anysize,
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/* b suffix on instruction illegal */
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No_bSuf,
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/* w suffix on instruction illegal */
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No_wSuf,
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/* l suffix on instruction illegal */
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No_lSuf,
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/* s suffix on instruction illegal */
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No_sSuf,
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/* q suffix on instruction illegal */
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No_qSuf,
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/* long double suffix on instruction illegal */
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No_ldSuf,
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/* instruction needs FWAIT */
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FWait,
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/* IsString provides for a quick test for string instructions, and
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its actual value also indicates which of the operands (if any)
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requires use of the %es segment. */
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#define IS_STRING_ES_OP0 2
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#define IS_STRING_ES_OP1 3
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IsString,
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/* RegMem is for instructions with a modrm byte where the register
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destination operand should be encoded in the mod and regmem fields.
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Normally, it will be encoded in the reg field. We add a RegMem
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flag to indicate that it should be encoded in the regmem field. */
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RegMem,
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/* quick test if branch instruction is MPX supported */
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BNDPrefixOk,
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/* quick test if NOTRACK prefix is supported */
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NoTrackPrefixOk,
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/* quick test for lockable instructions */
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IsLockable,
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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RegKludge,
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|
/* An implicit xmm0 as the first operand */
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Implicit1stXmm0,
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/* The HLE prefix is OK:
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1. With a LOCK prefix.
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2. With or without a LOCK prefix.
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3. With a RELEASE (0xf3) prefix.
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*/
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#define HLEPrefixNone 0
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#define HLEPrefixLock 1
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#define HLEPrefixAny 2
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#define HLEPrefixRelease 3
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HLEPrefixOk,
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/* An instruction on which a "rep" prefix is acceptable. */
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RepPrefixOk,
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/* Convert to DWORD */
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ToDword,
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/* Convert to QWORD */
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ToQword,
|
|
/* Address prefix changes register operand */
|
|
AddrPrefixOpReg,
|
|
/* opcode is a prefix */
|
|
IsPrefix,
|
|
/* instruction has extension in 8 bit imm */
|
|
ImmExt,
|
|
/* instruction don't need Rex64 prefix. */
|
|
NoRex64,
|
|
/* deprecated fp insn, gets a warning */
|
|
Ugh,
|
|
/* insn has VEX prefix:
|
|
1: 128bit VEX prefix (or operand dependent).
|
|
2: 256bit VEX prefix.
|
|
3: Scalar VEX prefix.
|
|
*/
|
|
#define VEX128 1
|
|
#define VEX256 2
|
|
#define VEXScalar 3
|
|
Vex,
|
|
/* How to encode VEX.vvvv:
|
|
0: VEX.vvvv must be 1111b.
|
|
1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
|
|
the content of source registers will be preserved.
|
|
VEX.DDS. The second register operand is encoded in VEX.vvvv
|
|
where the content of first source register will be overwritten
|
|
by the result.
|
|
VEX.NDD2. The second destination register operand is encoded in
|
|
VEX.vvvv for instructions with 2 destination register operands.
|
|
For assembler, there are no difference between VEX.NDS, VEX.DDS
|
|
and VEX.NDD2.
|
|
2. VEX.NDD. Register destination is encoded in VEX.vvvv for
|
|
instructions with 1 destination register operand.
|
|
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
|
|
of the operands can access a memory location.
|
|
*/
|
|
#define VEXXDS 1
|
|
#define VEXNDD 2
|
|
#define VEXLWP 3
|
|
VexVVVV,
|
|
/* How the VEX.W bit is used:
|
|
0: Set by the REX.W bit.
|
|
1: VEX.W0. Should always be 0.
|
|
2: VEX.W1. Should always be 1.
|
|
3: VEX.WIG. The VEX.W bit is ignored.
|
|
*/
|
|
#define VEXW0 1
|
|
#define VEXW1 2
|
|
#define VEXWIG 3
|
|
VexW,
|
|
/* VEX opcode prefix:
|
|
0: VEX 0x0F opcode prefix.
|
|
1: VEX 0x0F38 opcode prefix.
|
|
2: VEX 0x0F3A opcode prefix
|
|
3: XOP 0x08 opcode prefix.
|
|
4: XOP 0x09 opcode prefix
|
|
5: XOP 0x0A opcode prefix.
|
|
*/
|
|
#define VEX0F 0
|
|
#define VEX0F38 1
|
|
#define VEX0F3A 2
|
|
#define XOP08 3
|
|
#define XOP09 4
|
|
#define XOP0A 5
|
|
VexOpcode,
|
|
/* number of VEX source operands:
|
|
0: <= 2 source operands.
|
|
1: 2 XOP source operands.
|
|
2: 3 source operands.
|
|
*/
|
|
#define XOP2SOURCES 1
|
|
#define VEX3SOURCES 2
|
|
VexSources,
|
|
/* Instruction with vector SIB byte:
|
|
1: 128bit vector register.
|
|
2: 256bit vector register.
|
|
3: 512bit vector register.
|
|
*/
|
|
#define VecSIB128 1
|
|
#define VecSIB256 2
|
|
#define VecSIB512 3
|
|
VecSIB,
|
|
/* SSE to AVX support required */
|
|
SSE2AVX,
|
|
/* No AVX equivalent */
|
|
NoAVX,
|
|
|
|
/* insn has EVEX prefix:
|
|
1: 512bit EVEX prefix.
|
|
2: 128bit EVEX prefix.
|
|
3: 256bit EVEX prefix.
|
|
4: Length-ignored (LIG) EVEX prefix.
|
|
5: Length determined from actual operands.
|
|
*/
|
|
#define EVEX512 1
|
|
#define EVEX128 2
|
|
#define EVEX256 3
|
|
#define EVEXLIG 4
|
|
#define EVEXDYN 5
|
|
EVex,
|
|
|
|
/* AVX512 masking support:
|
|
1: Zeroing or merging masking depending on operands.
|
|
2: Merging-masking.
|
|
3: Both zeroing and merging masking.
|
|
*/
|
|
#define DYNAMIC_MASKING 1
|
|
#define MERGING_MASKING 2
|
|
#define BOTH_MASKING 3
|
|
Masking,
|
|
|
|
/* AVX512 broadcast support. The number of bytes to broadcast is
|
|
1 << (Broadcast - 1):
|
|
1: Byte broadcast.
|
|
2: Word broadcast.
|
|
3: Dword broadcast.
|
|
4: Qword broadcast.
|
|
*/
|
|
#define BYTE_BROADCAST 1
|
|
#define WORD_BROADCAST 2
|
|
#define DWORD_BROADCAST 3
|
|
#define QWORD_BROADCAST 4
|
|
Broadcast,
|
|
|
|
/* Static rounding control is supported. */
|
|
StaticRounding,
|
|
|
|
/* Supress All Exceptions is supported. */
|
|
SAE,
|
|
|
|
/* Compressed Disp8*N attribute. */
|
|
#define DISP8_SHIFT_VL 7
|
|
Disp8MemShift,
|
|
|
|
/* Default mask isn't allowed. */
|
|
NoDefMask,
|
|
|
|
/* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
|
|
It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
|
|
*/
|
|
ImplicitQuadGroup,
|
|
|
|
/* Support encoding optimization. */
|
|
Optimize,
|
|
|
|
/* AT&T mnemonic. */
|
|
ATTMnemonic,
|
|
/* AT&T syntax. */
|
|
ATTSyntax,
|
|
/* Intel syntax. */
|
|
IntelSyntax,
|
|
/* ISA64: Don't change the order without other code adjustments.
|
|
0: Common to AMD64 and Intel64.
|
|
1: AMD64.
|
|
2: Intel64.
|
|
3: Only in Intel64.
|
|
*/
|
|
#define AMD64 1
|
|
#define INTEL64 2
|
|
#define INTEL64ONLY 3
|
|
ISA64,
|
|
/* The last bitfield in i386_opcode_modifier. */
|
|
Opcode_Modifier_Num
|
|
};
|
|
|
|
typedef struct i386_opcode_modifier
|
|
{
|
|
unsigned int d:1;
|
|
unsigned int w:1;
|
|
unsigned int load:1;
|
|
unsigned int modrm:1;
|
|
unsigned int jump:3;
|
|
unsigned int floatmf:1;
|
|
unsigned int floatr:1;
|
|
unsigned int size:2;
|
|
unsigned int checkregsize:1;
|
|
unsigned int mnemonicsize:2;
|
|
unsigned int anysize:1;
|
|
unsigned int no_bsuf:1;
|
|
unsigned int no_wsuf:1;
|
|
unsigned int no_lsuf:1;
|
|
unsigned int no_ssuf:1;
|
|
unsigned int no_qsuf:1;
|
|
unsigned int no_ldsuf:1;
|
|
unsigned int fwait:1;
|
|
unsigned int isstring:2;
|
|
unsigned int regmem:1;
|
|
unsigned int bndprefixok:1;
|
|
unsigned int notrackprefixok:1;
|
|
unsigned int islockable:1;
|
|
unsigned int regkludge:1;
|
|
unsigned int implicit1stxmm0:1;
|
|
unsigned int hleprefixok:2;
|
|
unsigned int repprefixok:1;
|
|
unsigned int todword:1;
|
|
unsigned int toqword:1;
|
|
unsigned int addrprefixopreg:1;
|
|
unsigned int isprefix:1;
|
|
unsigned int immext:1;
|
|
unsigned int norex64:1;
|
|
unsigned int ugh:1;
|
|
unsigned int vex:2;
|
|
unsigned int vexvvvv:2;
|
|
unsigned int vexw:2;
|
|
unsigned int vexopcode:3;
|
|
unsigned int vexsources:2;
|
|
unsigned int vecsib:2;
|
|
unsigned int sse2avx:1;
|
|
unsigned int noavx:1;
|
|
unsigned int evex:3;
|
|
unsigned int masking:2;
|
|
unsigned int broadcast:3;
|
|
unsigned int staticrounding:1;
|
|
unsigned int sae:1;
|
|
unsigned int disp8memshift:3;
|
|
unsigned int nodefmask:1;
|
|
unsigned int implicitquadgroup:1;
|
|
unsigned int optimize:1;
|
|
unsigned int attmnemonic:1;
|
|
unsigned int attsyntax:1;
|
|
unsigned int intelsyntax:1;
|
|
unsigned int isa64:2;
|
|
} i386_opcode_modifier;
|
|
|
|
/* Operand classes. */
|
|
|
|
#define CLASS_WIDTH 4
|
|
enum operand_class
|
|
{
|
|
ClassNone,
|
|
Reg, /* GPRs and FP regs, distinguished by operand size */
|
|
SReg, /* Segment register */
|
|
RegCR, /* Control register */
|
|
RegDR, /* Debug register */
|
|
RegTR, /* Test register */
|
|
RegMMX, /* MMX register */
|
|
RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
|
|
RegMask, /* Vector Mask register */
|
|
RegBND, /* Bound register */
|
|
};
|
|
|
|
/* Special operand instances. */
|
|
|
|
#define INSTANCE_WIDTH 3
|
|
enum operand_instance
|
|
{
|
|
InstanceNone,
|
|
Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
|
|
RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
|
|
RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
|
|
RegB, /* %bl / %bx / %ebx / %rbx */
|
|
};
|
|
|
|
/* Position of operand_type bits. */
|
|
|
|
enum
|
|
{
|
|
/* Class and Instance */
|
|
ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
|
|
/* 1 bit immediate */
|
|
Imm1,
|
|
/* 8 bit immediate */
|
|
Imm8,
|
|
/* 8 bit immediate sign extended */
|
|
Imm8S,
|
|
/* 16 bit immediate */
|
|
Imm16,
|
|
/* 32 bit immediate */
|
|
Imm32,
|
|
/* 32 bit immediate sign extended */
|
|
Imm32S,
|
|
/* 64 bit immediate */
|
|
Imm64,
|
|
/* 8bit/16bit/32bit displacements are used in different ways,
|
|
depending on the instruction. For jumps, they specify the
|
|
size of the PC relative displacement, for instructions with
|
|
memory operand, they specify the size of the offset relative
|
|
to the base register, and for instructions with memory offset
|
|
such as `mov 1234,%al' they specify the size of the offset
|
|
relative to the segment base. */
|
|
/* 8 bit displacement */
|
|
Disp8,
|
|
/* 16 bit displacement */
|
|
Disp16,
|
|
/* 32 bit displacement */
|
|
Disp32,
|
|
/* 32 bit signed displacement */
|
|
Disp32S,
|
|
/* 64 bit displacement */
|
|
Disp64,
|
|
/* Register which can be used for base or index in memory operand. */
|
|
BaseIndex,
|
|
/* BYTE size. */
|
|
Byte,
|
|
/* WORD size. 2 byte */
|
|
Word,
|
|
/* DWORD size. 4 byte */
|
|
Dword,
|
|
/* FWORD size. 6 byte */
|
|
Fword,
|
|
/* QWORD size. 8 byte */
|
|
Qword,
|
|
/* TBYTE size. 10 byte */
|
|
Tbyte,
|
|
/* XMMWORD size. */
|
|
Xmmword,
|
|
/* YMMWORD size. */
|
|
Ymmword,
|
|
/* ZMMWORD size. */
|
|
Zmmword,
|
|
/* Unspecified memory size. */
|
|
Unspecified,
|
|
|
|
/* The number of bits in i386_operand_type. */
|
|
OTNum
|
|
};
|
|
|
|
#define OTNumOfUints \
|
|
((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
|
|
#define OTNumOfBits \
|
|
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
|
|
|
/* If you get a compiler error for zero width of the unused field,
|
|
comment it out. */
|
|
#define OTUnused OTNum
|
|
|
|
typedef union i386_operand_type
|
|
{
|
|
struct
|
|
{
|
|
unsigned int class:CLASS_WIDTH;
|
|
unsigned int instance:INSTANCE_WIDTH;
|
|
unsigned int imm1:1;
|
|
unsigned int imm8:1;
|
|
unsigned int imm8s:1;
|
|
unsigned int imm16:1;
|
|
unsigned int imm32:1;
|
|
unsigned int imm32s:1;
|
|
unsigned int imm64:1;
|
|
unsigned int disp8:1;
|
|
unsigned int disp16:1;
|
|
unsigned int disp32:1;
|
|
unsigned int disp32s:1;
|
|
unsigned int disp64:1;
|
|
unsigned int baseindex:1;
|
|
unsigned int byte:1;
|
|
unsigned int word:1;
|
|
unsigned int dword:1;
|
|
unsigned int fword:1;
|
|
unsigned int qword:1;
|
|
unsigned int tbyte:1;
|
|
unsigned int xmmword:1;
|
|
unsigned int ymmword:1;
|
|
unsigned int zmmword:1;
|
|
unsigned int unspecified:1;
|
|
#ifdef OTUnused
|
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
|
#endif
|
|
} bitfield;
|
|
unsigned int array[OTNumOfUints];
|
|
} i386_operand_type;
|
|
|
|
typedef struct insn_template
|
|
{
|
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
|
char *name;
|
|
|
|
/* base_opcode is the fundamental opcode byte without optional
|
|
prefix(es). */
|
|
unsigned int base_opcode;
|
|
#define Opcode_D 0x2 /* Direction bit:
|
|
set if Reg --> Regmem;
|
|
unset if Regmem --> Reg. */
|
|
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
|
|
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
|
|
#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
|
|
#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
|
|
|
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
|
This field is also used to store the 8-bit opcode suffix for the
|
|
AMD 3DNow! instructions.
|
|
If this template has no extension opcode (the usual case) use None
|
|
Instructions */
|
|
unsigned short extension_opcode;
|
|
#define None 0xffff /* If no extension_opcode is possible. */
|
|
|
|
/* Opcode length. */
|
|
unsigned char opcode_length;
|
|
|
|
/* how many operands */
|
|
unsigned char operands;
|
|
|
|
/* cpu feature flags */
|
|
i386_cpu_flags cpu_flags;
|
|
|
|
/* the bits in opcode_modifier are used to generate the final opcode from
|
|
the base_opcode. These bits also are used to detect alternate forms of
|
|
the same instruction */
|
|
i386_opcode_modifier opcode_modifier;
|
|
|
|
/* operand_types[i] describes the type of operand i. This is made
|
|
by OR'ing together all of the possible type masks. (e.g.
|
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
|
either a register or an immediate operand. */
|
|
i386_operand_type operand_types[MAX_OPERANDS];
|
|
}
|
|
insn_template;
|
|
|
|
extern const insn_template i386_optab[];
|
|
|
|
/* these are for register name --> number & type hash lookup */
|
|
typedef struct
|
|
{
|
|
char *reg_name;
|
|
i386_operand_type reg_type;
|
|
unsigned char reg_flags;
|
|
#define RegRex 0x1 /* Extended register. */
|
|
#define RegRex64 0x2 /* Extended 8 bit register. */
|
|
#define RegVRex 0x4 /* Extended vector register. */
|
|
unsigned char reg_num;
|
|
#define RegIP ((unsigned char ) ~0)
|
|
/* EIZ and RIZ are fake index registers. */
|
|
#define RegIZ (RegIP - 1)
|
|
/* FLAT is a fake segment register (Intel mode). */
|
|
#define RegFlat ((unsigned char) ~0)
|
|
signed char dw2_regnum[2];
|
|
#define Dw2Inval (-1)
|
|
}
|
|
reg_entry;
|
|
|
|
/* Entries in i386_regtab. */
|
|
#define REGNAM_AL 1
|
|
#define REGNAM_AX 25
|
|
#define REGNAM_EAX 41
|
|
|
|
extern const reg_entry i386_regtab[];
|
|
extern const unsigned int i386_regtab_size;
|
|
|
|
typedef struct
|
|
{
|
|
char *seg_name;
|
|
unsigned int seg_prefix;
|
|
}
|
|
seg_entry;
|
|
|
|
extern const seg_entry cs;
|
|
extern const seg_entry ds;
|
|
extern const seg_entry ss;
|
|
extern const seg_entry es;
|
|
extern const seg_entry fs;
|
|
extern const seg_entry gs;
|