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1098 lines
22 KiB
C
1098 lines
22 KiB
C
/* Simulator for Xilinx MicroBlaze processor
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Copyright 2009-2012 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include <signal.h>
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#include "sysdep.h"
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#include <sys/times.h>
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#include <sys/param.h>
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#include <netinet/in.h> /* for byte ordering macros */
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#include "bfd.h"
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#include "gdb/callback.h"
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#include "libiberty.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-utils.h"
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#include "microblaze-dis.h"
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#ifndef NUM_ELEM
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#define NUM_ELEM(A) (sizeof (A) / sizeof (A)[0])
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#endif
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static int target_big_endian = 1;
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static unsigned long heap_ptr = 0;
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static unsigned long stack_ptr = 0;
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host_callback *callback;
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unsigned long
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microblaze_extract_unsigned_integer (unsigned char *addr, int len)
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{
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unsigned long retval;
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (len > (int) sizeof (unsigned long))
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printf ("That operation is not available on integers of more than "
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"%d bytes.", sizeof (unsigned long));
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/* Start at the most significant end of the integer, and work towards
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the least significant. */
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retval = 0;
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if (!target_big_endian)
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{
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for (p = endaddr; p > startaddr;)
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retval = (retval << 8) | * -- p;
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}
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else
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{
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for (p = startaddr; p < endaddr;)
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retval = (retval << 8) | * p ++;
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}
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return retval;
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}
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void
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microblaze_store_unsigned_integer (unsigned char *addr, int len,
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unsigned long val)
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{
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (!target_big_endian)
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{
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for (p = startaddr; p < endaddr;)
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{
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*p++ = val & 0xff;
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val >>= 8;
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}
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}
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else
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{
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for (p = endaddr; p > startaddr;)
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{
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*--p = val & 0xff;
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val >>= 8;
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}
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}
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}
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struct sim_state microblaze_state;
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int memcycles = 1;
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static SIM_OPEN_KIND sim_kind;
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static char *myname;
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static int issue_messages = 0;
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long
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int_sbrk (int inc_bytes)
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{
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long addr;
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addr = heap_ptr;
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heap_ptr += inc_bytes;
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if (issue_messages && heap_ptr > SP)
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fprintf (stderr, "Warning: heap_ptr overlaps stack!\n");
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return addr;
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}
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static void /* INLINE */
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wbat (word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v;
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}
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}
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static void /* INLINE */
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wlat (word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word write to unaligned memory address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[3] = v >> 24;
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p[2] = v >> 16;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 24;
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p[1] = v >> 16;
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p[2] = v >> 8;
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p[3] = v;
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}
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}
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}
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static void /* INLINE */
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what (word x, word v)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short write to 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short write to unaligned memory address: 0x%x\n",
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x);
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CPU.exception = SIGBUS;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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p[1] = v >> 8;
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p[0] = v;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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p[0] = v >> 8;
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p[1] = v;
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}
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}
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}
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/* Read functions. */
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static int /* INLINE */
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rbat (word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "byte read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return p[0];
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}
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}
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static int /* INLINE */
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rlat (word x)
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{
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if (((uword) x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "word read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 3) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "word read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (! target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
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}
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}
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}
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static int /* INLINE */
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rhat (word x)
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{
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if (((uword)x) >= CPU.msize)
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{
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if (issue_messages)
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fprintf (stderr, "short read from 0x%x outside memory range\n", x);
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CPU.exception = SIGSEGV;
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return 0;
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}
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else
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{
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if ((x & 1) != 0)
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{
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if (issue_messages)
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fprintf (stderr, "short read from unaligned address: 0x%x\n", x);
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CPU.exception = SIGBUS;
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return 0;
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}
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else if (!target_big_endian)
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{
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unsigned char *p = CPU.memory + x;
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return (p[1] << 8) | p[0];
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}
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else
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{
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unsigned char *p = CPU.memory + x;
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return (p[0] << 8) | p[1];
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}
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}
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}
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#define SEXTB(x) (((x & 0xff) ^ (~ 0x7f)) + 0x80)
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#define SEXTW(y) ((int)((short)y))
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static int
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IOMEM (int addr, int write, int value)
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{
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}
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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static int sim_memory_size = 1 << 23;
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#define MEM_SIZE_FLOOR 64
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void
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sim_size (int size)
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{
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sim_memory_size = size;
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CPU.msize = sim_memory_size;
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if (CPU.memory)
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free (CPU.memory);
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CPU.memory = (unsigned char *) calloc (1, CPU.msize);
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if (!CPU.memory)
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{
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if (issue_messages)
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fprintf (stderr,
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"Not enough VM for simulation of %d bytes of RAM\n",
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CPU.msize);
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CPU.msize = 1;
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CPU.memory = (unsigned char *) calloc (1, 1);
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}
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}
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static void
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init_pointers ()
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{
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if (CPU.msize != (sim_memory_size))
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sim_size (sim_memory_size);
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}
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static void
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set_initial_gprs ()
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{
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int i;
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long space;
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unsigned long memsize;
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init_pointers ();
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/* Set up machine just out of reset. */
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PC = 0;
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MSR = 0;
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memsize = CPU.msize / (1024 * 1024);
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if (issue_messages > 1)
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fprintf (stderr, "Simulated memory of %d Mbytes (0x0 .. 0x%08x)\n",
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memsize, CPU.msize - 1);
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/* Clean out the GPRs */
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for (i = 0; i < 32; i++)
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CPU.regs[i] = 0;
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CPU.insts = 0;
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CPU.cycles = 0;
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CPU.imm_enable = 0;
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}
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static void
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interrupt ()
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{
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CPU.exception = SIGINT;
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}
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/* Functions so that trapped open/close don't interfere with the
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parent's functions. We say that we can't close the descriptors
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that we didn't open. exit() and cleanup() get in trouble here,
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to some extent. That's the price of emulation. */
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unsigned char opened[100];
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static void
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log_open (int fd)
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{
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if (fd < 0 || fd > NUM_ELEM (opened))
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return;
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opened[fd] = 1;
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}
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static void
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log_close (int fd)
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{
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if (fd < 0 || fd > NUM_ELEM (opened))
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return;
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opened[fd] = 0;
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}
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static int
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is_opened (int fd)
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{
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if (fd < 0 || fd > NUM_ELEM (opened))
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return 0;
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return opened[fd];
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}
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static void
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handle_trap1 ()
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{
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}
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static void
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process_stub (int what)
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{
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/* These values should match those in libgloss/microblaze/syscalls.s. */
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switch (what)
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{
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case 3: /* _read */
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case 4: /* _write */
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case 5: /* _open */
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case 6: /* _close */
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case 10: /* _unlink */
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case 19: /* _lseek */
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case 43: /* _times */
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handle_trap1 ();
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break;
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default:
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if (issue_messages)
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fprintf (stderr, "Unhandled stub opcode: %d\n", what);
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break;
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}
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}
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static void
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util (unsigned what)
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{
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switch (what)
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{
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case 0: /* exit */
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CPU.exception = SIGQUIT;
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break;
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case 1: /* printf */
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{
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unsigned long a[6];
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unsigned char *s;
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int i;
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for (s = (unsigned char *)a[0], i = 1 ; *s && i < 6 ; s++)
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if (*s == '%')
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i++;
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}
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break;
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case 2: /* scanf */
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if (issue_messages)
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fprintf (stderr, "WARNING: scanf unimplemented\n");
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break;
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case 3: /* utime */
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break;
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case 0xFF:
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process_stub (CPU.regs[1]);
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break;
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default:
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if (issue_messages)
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fprintf (stderr, "Unhandled util code: %x\n", what);
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break;
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}
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}
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/* For figuring out whether we carried; addc/subc use this. */
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static int
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iu_carry (unsigned long a, unsigned long b, int cin)
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{
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unsigned long x;
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x = (a & 0xffff) + (b & 0xffff) + cin;
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x = (x >> 16) + (a >> 16) + (b >> 16);
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x >>= 16;
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return (x != 0);
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}
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#define WATCHFUNCTIONS 1
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#ifdef WATCHFUNCTIONS
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#define MAXWL 80
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word WL[MAXWL];
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char *WLstr[MAXWL];
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int ENDWL=0;
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int WLincyc;
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int WLcyc[MAXWL];
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int WLcnts[MAXWL];
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int WLmax[MAXWL];
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int WLmin[MAXWL];
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word WLendpc;
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int WLbcyc;
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int WLW;
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#endif
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static int tracing = 0;
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void
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sim_resume (SIM_DESC sd, int step, int siggnal)
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{
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int needfetch;
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word inst;
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enum microblaze_instr op;
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void (*sigsave)();
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int memops;
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int bonus_cycles;
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int insts;
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int w;
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int cycs;
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word WLhash;
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ubyte carry;
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int imm_unsigned;
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short ra, rb, rd;
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long immword;
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uword oldpc, newpc;
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short delay_slot_enable;
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short branch_taken;
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short num_delay_slot; /* UNUSED except as reqd parameter */
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enum microblaze_instr_type insn_type;
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sigsave = signal (SIGINT, interrupt);
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CPU.exception = step ? SIGTRAP : 0;
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memops = 0;
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bonus_cycles = 0;
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insts = 0;
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|
do
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{
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/* Fetch the initial instructions that we'll decode. */
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inst = rlat (PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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fprintf (stderr, "Unknown instruction 0x%04x", inst);
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if (tracing)
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fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
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rd = GET_RD;
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rb = GET_RB;
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ra = GET_RA;
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/* immword = IMM_W; */
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oldpc = PC;
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delay_slot_enable = 0;
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branch_taken = 0;
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if (op == microblaze_brk)
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CPU.exception = SIGTRAP;
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else if (inst == MICROBLAZE_HALT_INST)
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{
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CPU.exception = SIGQUIT;
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insts += 1;
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bonus_cycles++;
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|
}
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|
else
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|
{
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switch(op)
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|
{
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|
#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
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case NAME: \
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ACTION; \
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break;
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#include "microblaze.isa"
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|
#undef INSTRUCTION
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|
|
default:
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CPU.exception = SIGILL;
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|
fprintf (stderr, "ERROR: Unknown opcode\n");
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}
|
|
/* Make R0 consistent */
|
|
CPU.regs[0] = 0;
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|
|
/* Check for imm instr */
|
|
if (op == imm)
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|
IMM_ENABLE = 1;
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|
else
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|
IMM_ENABLE = 0;
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|
|
/* Update cycle counts */
|
|
insts ++;
|
|
if (insn_type == memory_store_inst || insn_type == memory_load_inst)
|
|
memops++;
|
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if (insn_type == mult_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == barrel_shift_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == anyware_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == div_inst)
|
|
bonus_cycles += 33;
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|
|
if ((insn_type == branch_inst || insn_type == return_inst)
|
|
&& branch_taken)
|
|
{
|
|
/* Add an extra cycle for taken branches */
|
|
bonus_cycles++;
|
|
/* For branch instructions handle the instruction in the delay slot */
|
|
if (delay_slot_enable)
|
|
{
|
|
newpc = PC;
|
|
PC = oldpc + INST_SIZE;
|
|
inst = rlat (PC & 0xFFFFFFFC);
|
|
op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
|
|
&num_delay_slot);
|
|
if (op == invalid_inst)
|
|
fprintf (stderr, "Unknown instruction 0x%04x", inst);
|
|
if (tracing)
|
|
fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
|
|
rd = GET_RD;
|
|
rb = GET_RB;
|
|
ra = GET_RA;
|
|
/* immword = IMM_W; */
|
|
if (op == microblaze_brk)
|
|
{
|
|
if (issue_messages)
|
|
fprintf (stderr, "Breakpoint set in delay slot "
|
|
"(at address 0x%x) will not be honored\n", PC);
|
|
/* ignore the breakpoint */
|
|
}
|
|
else if (insn_type == branch_inst || insn_type == return_inst)
|
|
{
|
|
if (issue_messages)
|
|
fprintf (stderr, "Cannot have branch or return instructions "
|
|
"in delay slot (at address 0x%x)\n", PC);
|
|
CPU.exception = SIGILL;
|
|
}
|
|
else
|
|
{
|
|
switch(op)
|
|
{
|
|
#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
|
|
case NAME: \
|
|
ACTION; \
|
|
break;
|
|
#include "microblaze.isa"
|
|
#undef INSTRUCTION
|
|
|
|
default:
|
|
CPU.exception = SIGILL;
|
|
fprintf (stderr, "ERROR: Unknown opcode at 0x%x\n", PC);
|
|
}
|
|
/* Update cycle counts */
|
|
insts++;
|
|
if (insn_type == memory_store_inst
|
|
|| insn_type == memory_load_inst)
|
|
memops++;
|
|
if (insn_type == mult_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == barrel_shift_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == anyware_inst)
|
|
bonus_cycles++;
|
|
if (insn_type == div_inst)
|
|
bonus_cycles += 33;
|
|
}
|
|
/* Restore the PC */
|
|
PC = newpc;
|
|
/* Make R0 consistent */
|
|
CPU.regs[0] = 0;
|
|
/* Check for imm instr */
|
|
if (op == imm)
|
|
IMM_ENABLE = 1;
|
|
else
|
|
IMM_ENABLE = 0;
|
|
}
|
|
else
|
|
/* no delay slot: increment cycle count */
|
|
bonus_cycles++;
|
|
}
|
|
}
|
|
|
|
if (tracing)
|
|
fprintf (stderr, "\n");
|
|
}
|
|
while (!CPU.exception);
|
|
|
|
/* Hide away the things we've cached while executing. */
|
|
/* CPU.pc = pc; */
|
|
CPU.insts += insts; /* instructions done ... */
|
|
CPU.cycles += insts; /* and each takes a cycle */
|
|
CPU.cycles += bonus_cycles; /* and extra cycles for branches */
|
|
CPU.cycles += memops; /* and memop cycle delays */
|
|
|
|
signal (SIGINT, sigsave);
|
|
}
|
|
|
|
|
|
int
|
|
sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
|
|
{
|
|
int i;
|
|
init_pointers ();
|
|
|
|
memcpy (&CPU.memory[addr], buffer, size);
|
|
|
|
return size;
|
|
}
|
|
|
|
int
|
|
sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
|
|
{
|
|
int i;
|
|
init_pointers ();
|
|
|
|
memcpy (buffer, &CPU.memory[addr], size);
|
|
|
|
return size;
|
|
}
|
|
|
|
|
|
int
|
|
sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
|
|
{
|
|
init_pointers ();
|
|
|
|
if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
|
|
{
|
|
if (length == 4)
|
|
{
|
|
/* misalignment safe */
|
|
long ival = microblaze_extract_unsigned_integer (memory, 4);
|
|
if (rn < NUM_REGS)
|
|
CPU.regs[rn] = ival;
|
|
else
|
|
CPU.spregs[rn-NUM_REGS] = ival;
|
|
return 4;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
|
|
{
|
|
long ival;
|
|
init_pointers ();
|
|
|
|
if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
|
|
{
|
|
if (length == 4)
|
|
{
|
|
if (rn < NUM_REGS)
|
|
ival = CPU.regs[rn];
|
|
else
|
|
ival = CPU.spregs[rn-NUM_REGS];
|
|
|
|
/* misalignment-safe */
|
|
microblaze_store_unsigned_integer (memory, 4, ival);
|
|
return 4;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
|
|
int
|
|
sim_trace (SIM_DESC sd)
|
|
{
|
|
tracing = 1;
|
|
|
|
sim_resume (sd, 0, 0);
|
|
|
|
tracing = 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
|
|
{
|
|
if (CPU.exception == SIGQUIT)
|
|
{
|
|
*reason = sim_exited;
|
|
*sigrc = RETREG;
|
|
}
|
|
else
|
|
{
|
|
*reason = sim_stopped;
|
|
*sigrc = CPU.exception;
|
|
}
|
|
}
|
|
|
|
|
|
int
|
|
sim_stop (SIM_DESC sd)
|
|
{
|
|
CPU.exception = SIGINT;
|
|
return 1;
|
|
}
|
|
|
|
|
|
void
|
|
sim_info (SIM_DESC sd, int verbose)
|
|
{
|
|
#ifdef WATCHFUNCTIONS
|
|
int w, wcyc;
|
|
#endif
|
|
|
|
callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
|
|
CPU.insts);
|
|
callback->printf_filtered (callback, "# cycles %10d\n",
|
|
(CPU.cycles) ? CPU.cycles+2 : 0);
|
|
|
|
#ifdef WATCHFUNCTIONS
|
|
callback->printf_filtered (callback, "\nNumber of watched functions: %d\n",
|
|
ENDWL);
|
|
|
|
wcyc = 0;
|
|
|
|
for (w = 1; w <= ENDWL; w++)
|
|
{
|
|
callback->printf_filtered (callback, "WL = %s %8x\n",WLstr[w],WL[w]);
|
|
callback->printf_filtered (callback, " calls = %d, cycles = %d\n",
|
|
WLcnts[w],WLcyc[w]);
|
|
|
|
if (WLcnts[w] != 0)
|
|
callback->printf_filtered (callback,
|
|
" maxcpc = %d, mincpc = %d, avecpc = %d\n",
|
|
WLmax[w],WLmin[w],WLcyc[w]/WLcnts[w]);
|
|
wcyc += WLcyc[w];
|
|
}
|
|
|
|
callback->printf_filtered (callback,
|
|
"Total cycles for watched functions: %d\n",wcyc);
|
|
#endif
|
|
}
|
|
|
|
struct aout
|
|
{
|
|
unsigned char sa_machtype[2];
|
|
unsigned char sa_magic[2];
|
|
unsigned char sa_tsize[4];
|
|
unsigned char sa_dsize[4];
|
|
unsigned char sa_bsize[4];
|
|
unsigned char sa_syms[4];
|
|
unsigned char sa_entry[4];
|
|
unsigned char sa_trelo[4];
|
|
unsigned char sa_drelo[4];
|
|
} aout;
|
|
|
|
#define LONG(x) (((x)[0]<<24)|((x)[1]<<16)|((x)[2]<<8)|(x)[3])
|
|
#define SHORT(x) (((x)[0]<<8)|(x)[1])
|
|
|
|
SIM_DESC
|
|
sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
|
|
{
|
|
/* SIM_DESC sd = sim_state_alloc(kind, alloc);*/
|
|
|
|
int osize = sim_memory_size;
|
|
myname = argv[0];
|
|
callback = cb;
|
|
|
|
if (kind == SIM_OPEN_STANDALONE)
|
|
issue_messages = 1;
|
|
|
|
/* Discard and reacquire memory -- start with a clean slate. */
|
|
sim_size (1); /* small */
|
|
sim_size (osize); /* and back again */
|
|
|
|
set_initial_gprs (); /* Reset the GPR registers. */
|
|
|
|
return ((SIM_DESC) 1);
|
|
}
|
|
|
|
void
|
|
sim_close (SIM_DESC sd, int quitting)
|
|
{
|
|
if (CPU.memory)
|
|
{
|
|
free(CPU.memory);
|
|
CPU.memory = NULL;
|
|
CPU.msize = 0;
|
|
}
|
|
}
|
|
|
|
SIM_RC
|
|
sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty)
|
|
{
|
|
/* Do the right thing for ELF executables; this turns out to be
|
|
just about the right thing for any object format that:
|
|
- we crack using BFD routines
|
|
- follows the traditional UNIX text/data/bss layout
|
|
- calls the bss section ".bss". */
|
|
|
|
extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
|
|
bfd *prog_bfd;
|
|
|
|
{
|
|
bfd *handle;
|
|
asection *s;
|
|
int found_loadable_section = 0;
|
|
bfd_vma max_addr = 0;
|
|
handle = bfd_openr (prog, 0);
|
|
|
|
if (!handle)
|
|
{
|
|
printf("``%s'' could not be opened.\n", prog);
|
|
return SIM_RC_FAIL;
|
|
}
|
|
|
|
/* Makes sure that we have an object file, also cleans gets the
|
|
section headers in place. */
|
|
if (!bfd_check_format (handle, bfd_object))
|
|
{
|
|
/* wasn't an object file */
|
|
bfd_close (handle);
|
|
printf ("``%s'' is not appropriate object file.\n", prog);
|
|
return SIM_RC_FAIL;
|
|
}
|
|
|
|
for (s = handle->sections; s; s = s->next)
|
|
{
|
|
if (s->flags & SEC_ALLOC)
|
|
{
|
|
bfd_vma vma = 0;
|
|
int size = bfd_get_section_size (s);
|
|
if (size > 0)
|
|
{
|
|
vma = bfd_section_vma (handle, s);
|
|
if (vma >= max_addr)
|
|
{
|
|
max_addr = vma + size;
|
|
}
|
|
}
|
|
if (s->flags & SEC_LOAD)
|
|
found_loadable_section = 1;
|
|
}
|
|
}
|
|
|
|
if (!found_loadable_section)
|
|
{
|
|
/* No loadable sections */
|
|
bfd_close(handle);
|
|
printf("No loadable sections in file %s\n", prog);
|
|
return SIM_RC_FAIL;
|
|
}
|
|
|
|
sim_memory_size = (unsigned long) max_addr;
|
|
|
|
/* Clean up after ourselves. */
|
|
bfd_close (handle);
|
|
|
|
}
|
|
|
|
/* from sh -- dac */
|
|
prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
|
|
/* sim_kind == SIM_OPEN_DEBUG, */
|
|
1,
|
|
0, sim_write);
|
|
if (prog_bfd == NULL)
|
|
return SIM_RC_FAIL;
|
|
|
|
target_big_endian = bfd_big_endian (prog_bfd);
|
|
PC = bfd_get_start_address (prog_bfd);
|
|
|
|
if (abfd == NULL)
|
|
bfd_close (prog_bfd);
|
|
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
|
|
{
|
|
char **avp;
|
|
int nargs = 0;
|
|
int nenv = 0;
|
|
int s_length;
|
|
int l;
|
|
unsigned long strings;
|
|
unsigned long pointers;
|
|
unsigned long hi_stack;
|
|
|
|
|
|
/* Set the initial register set. */
|
|
l = issue_messages;
|
|
issue_messages = 0;
|
|
set_initial_gprs ();
|
|
issue_messages = l;
|
|
|
|
hi_stack = CPU.msize - 4;
|
|
PC = bfd_get_start_address (prog_bfd);
|
|
|
|
/* For now ignore all parameters to the program */
|
|
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
void
|
|
sim_kill (SIM_DESC sd)
|
|
{
|
|
/* nothing to do */
|
|
}
|
|
|
|
void
|
|
sim_do_command (SIM_DESC sd, char * cmd)
|
|
{
|
|
/* Nothing there yet; it's all an error. */
|
|
|
|
if (cmd != NULL)
|
|
{
|
|
char ** simargv = buildargv (cmd);
|
|
|
|
if (strcmp (simargv[0], "watch") == 0)
|
|
{
|
|
if ((simargv[1] == NULL) || (simargv[2] == NULL))
|
|
{
|
|
fprintf (stderr, "Error: missing argument to watch cmd.\n");
|
|
return;
|
|
}
|
|
|
|
ENDWL++;
|
|
|
|
WL[ENDWL] = strtol (simargv[2], NULL, 0);
|
|
WLstr[ENDWL] = strdup (simargv[1]);
|
|
fprintf (stderr, "Added %s (%x) to watchlist, #%d\n",WLstr[ENDWL],
|
|
WL[ENDWL], ENDWL);
|
|
|
|
}
|
|
else if (strcmp (simargv[0], "dumpmem") == 0)
|
|
{
|
|
unsigned char * p;
|
|
FILE * dumpfile;
|
|
|
|
if (simargv[1] == NULL)
|
|
fprintf (stderr, "Error: missing argument to dumpmem cmd.\n");
|
|
|
|
fprintf (stderr, "Writing dumpfile %s...",simargv[1]);
|
|
|
|
dumpfile = fopen (simargv[1], "w");
|
|
p = CPU.memory;
|
|
fwrite (p, CPU.msize-1, 1, dumpfile);
|
|
fclose (dumpfile);
|
|
|
|
fprintf (stderr, "done.\n");
|
|
}
|
|
else if (strcmp (simargv[0], "clearstats") == 0)
|
|
{
|
|
CPU.cycles = 0;
|
|
CPU.insts = 0;
|
|
ENDWL = 0;
|
|
}
|
|
else if (strcmp (simargv[0], "verbose") == 0)
|
|
{
|
|
issue_messages = 2;
|
|
}
|
|
else
|
|
{
|
|
fprintf (stderr,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
|
|
cmd);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
fprintf (stderr, "M.CORE sim commands: \n");
|
|
fprintf (stderr, " watch <funcname> <addr>\n");
|
|
fprintf (stderr, " dumpmem <filename>\n");
|
|
fprintf (stderr, " clearstats\n");
|
|
fprintf (stderr, " verbose\n");
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_set_callbacks (host_callback *ptr)
|
|
{
|
|
callback = ptr;
|
|
}
|
|
|
|
char **
|
|
sim_complete_command (SIM_DESC sd, char *text, char *word)
|
|
{
|
|
return NULL;
|
|
}
|