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binutils-gdb/sim/example-synacor
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Mike Frysinger aa0fca163e sim: add support for build-time ar & ranlib 
This is needed when building for a target whose ar & ranlib are
incompatible with the current build system.  For example, building
for Windows on a Linux system.

Then manually import the automake rule for libigen.a, but tweak the
tool variables to use the FOR_BUILD variants.
2021-05-04 08:22:07 -04:00
..
aclocal.m4 sim: enable hardware support by default 2021-04-26 22:30:55 -04:00
ChangeLog sim: add support for build-time ar & ranlib 2021-05-04 08:22:07 -04:00
config.in sim: nrun: add local strsignal prototype 2021-05-01 16:37:39 -04:00
configure sim: add support for build-time ar & ranlib 2021-05-04 08:22:07 -04:00
configure.ac
interp.c
Makefile.in
README
README.arch-spec
sim-main.c
sim-main.h

README 

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.