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535 lines
15 KiB
C++
535 lines
15 KiB
C++
// mips.h -- ELF definitions specific to EM_MIPS -*- C++ -*-
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// Copyright (C) 2012-2021 Free Software Foundation, Inc.
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// Written by Sasa Stankovic <sasa.stankovic@imgtec.com>
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// and Aleksandar Simeonov <aleksandar.simeonov@rt-rk.com>.
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// This file is part of elfcpp.
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Library General Public License
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// as published by the Free Software Foundation; either version 2, or
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// (at your option) any later version.
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// In addition to the permissions in the GNU Library General Public
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// License, the Free Software Foundation gives you unlimited
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// permission to link the compiled version of this file into
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// combinations with other programs, and to distribute those
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// combinations without any restriction coming from the use of this
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// file. (The Library Public License restrictions do apply in other
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// respects; for example, they cover modification of the file, and
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/// distribution when not linked into a combined executable.)
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// This program is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Library General Public License for more details.
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// You should have received a copy of the GNU Library General Public
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// License along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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#ifndef ELFCPP_MIPS_H
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#define ELFCPP_MIPS_H
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// Documentation for the MIPS relocs is taken from
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// http://math-atlas.sourceforge.net/devel/assembly/mipsabi32.pdf
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namespace elfcpp
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{
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//
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// MIPS Relocation Codes
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//
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enum
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{
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R_MIPS_NONE = 0,
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R_MIPS_16 = 1,
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R_MIPS_32 = 2, // In Elf 64: alias R_MIPS_ADD
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R_MIPS_REL32 = 3, // In Elf 64: alias R_MIPS_REL
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R_MIPS_26 = 4,
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R_MIPS_HI16 = 5,
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R_MIPS_LO16 = 6,
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R_MIPS_GPREL16 = 7, // In Elf 64: alias R_MIPS_GPREL
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R_MIPS_LITERAL = 8,
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R_MIPS_GOT16 = 9, // In Elf 64: alias R_MIPS_GOT
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R_MIPS_PC16 = 10,
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R_MIPS_CALL16 = 11, // In Elf 64: alias R_MIPS_CALL
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R_MIPS_GPREL32 = 12,
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R_MIPS_UNUSED1 = 13,
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R_MIPS_UNUSED2 = 14,
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R_MIPS_UNUSED3 = 15,
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R_MIPS_SHIFT5 = 16,
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R_MIPS_SHIFT6 = 17,
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R_MIPS_64 = 18,
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R_MIPS_GOT_DISP = 19,
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R_MIPS_GOT_PAGE = 20,
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R_MIPS_GOT_OFST = 21,
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R_MIPS_GOT_HI16 = 22,
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R_MIPS_GOT_LO16 = 23,
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R_MIPS_SUB = 24,
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R_MIPS_INSERT_A = 25,
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R_MIPS_INSERT_B = 26,
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R_MIPS_DELETE = 27,
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R_MIPS_HIGHER = 28,
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R_MIPS_HIGHEST = 29,
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R_MIPS_CALL_HI16 = 30,
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R_MIPS_CALL_LO16 = 31,
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R_MIPS_SCN_DISP = 32,
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R_MIPS_REL16 = 33,
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R_MIPS_ADD_IMMEDIATE = 34,
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R_MIPS_PJUMP = 35,
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R_MIPS_RELGOT = 36,
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R_MIPS_JALR = 37,
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// TLS relocations.
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R_MIPS_TLS_DTPMOD32 = 38,
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R_MIPS_TLS_DTPREL32 = 39,
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R_MIPS_TLS_DTPMOD64 = 40,
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R_MIPS_TLS_DTPREL64 = 41,
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R_MIPS_TLS_GD = 42,
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R_MIPS_TLS_LDM = 43,
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R_MIPS_TLS_DTPREL_HI16 = 44,
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R_MIPS_TLS_DTPREL_LO16 = 45,
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R_MIPS_TLS_GOTTPREL = 46,
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R_MIPS_TLS_TPREL32 = 47,
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R_MIPS_TLS_TPREL64 = 48,
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R_MIPS_TLS_TPREL_HI16 = 49,
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R_MIPS_TLS_TPREL_LO16 = 50,
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R_MIPS_GLOB_DAT = 51,
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R_MIPS_PC21_S2 = 60,
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R_MIPS_PC26_S2 = 61,
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R_MIPS_PC18_S3 = 62,
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R_MIPS_PC19_S2 = 63,
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R_MIPS_PCHI16 = 64,
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R_MIPS_PCLO16 = 65,
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// These relocs are used for the mips16.
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R_MIPS16_26 = 100,
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R_MIPS16_GPREL = 101,
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R_MIPS16_GOT16 = 102,
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R_MIPS16_CALL16 = 103,
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R_MIPS16_HI16 = 104,
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R_MIPS16_LO16 = 105,
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R_MIPS16_TLS_GD = 106,
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R_MIPS16_TLS_LDM = 107,
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R_MIPS16_TLS_DTPREL_HI16 = 108,
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R_MIPS16_TLS_DTPREL_LO16 = 109,
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R_MIPS16_TLS_GOTTPREL = 110,
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R_MIPS16_TLS_TPREL_HI16 = 111,
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R_MIPS16_TLS_TPREL_LO16 = 112,
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R_MIPS_COPY = 126,
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R_MIPS_JUMP_SLOT = 127,
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// These relocations are specific to microMIPS.
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R_MICROMIPS_26_S1 = 133,
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R_MICROMIPS_HI16 = 134,
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R_MICROMIPS_LO16 = 135,
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R_MICROMIPS_GPREL16 = 136, // In Elf 64: alias R_MICROMIPS_GPREL
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R_MICROMIPS_LITERAL = 137,
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R_MICROMIPS_GOT16 = 138, // In Elf 64: alias R_MICROMIPS_GOT
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R_MICROMIPS_PC7_S1 = 139,
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R_MICROMIPS_PC10_S1 = 140,
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R_MICROMIPS_PC16_S1 = 141,
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R_MICROMIPS_CALL16 = 142, // In Elf 64: alias R_MICROMIPS_CALL
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R_MICROMIPS_GOT_DISP = 145,
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R_MICROMIPS_GOT_PAGE = 146,
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R_MICROMIPS_GOT_OFST = 147,
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R_MICROMIPS_GOT_HI16 = 148,
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R_MICROMIPS_GOT_LO16 = 149,
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R_MICROMIPS_SUB = 150,
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R_MICROMIPS_HIGHER = 151,
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R_MICROMIPS_HIGHEST = 152,
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R_MICROMIPS_CALL_HI16 = 153,
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R_MICROMIPS_CALL_LO16 = 154,
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R_MICROMIPS_SCN_DISP = 155,
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R_MICROMIPS_JALR = 156,
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R_MICROMIPS_HI0_LO16 = 157,
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// TLS relocations.
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R_MICROMIPS_TLS_GD = 162,
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R_MICROMIPS_TLS_LDM = 163,
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R_MICROMIPS_TLS_DTPREL_HI16 = 164,
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R_MICROMIPS_TLS_DTPREL_LO16 = 165,
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R_MICROMIPS_TLS_GOTTPREL = 166,
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R_MICROMIPS_TLS_TPREL_HI16 = 169,
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R_MICROMIPS_TLS_TPREL_LO16 = 170,
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// microMIPS GP- and PC-relative relocations.
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R_MICROMIPS_GPREL7_S2 = 172,
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R_MICROMIPS_PC23_S2 = 173,
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// This was a GNU extension used by embedded-PIC. It was co-opted by
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// mips-linux for exception-handling data. GCC stopped using it in
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// May, 2004, then started using it again for compact unwind tables.
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R_MIPS_PC32 = 248,
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R_MIPS_EH = 249,
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// This relocation is used internally by gas.
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R_MIPS_GNU_REL16_S2 = 250,
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// These are GNU extensions to enable C++ vtable garbage collection.
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R_MIPS_GNU_VTINHERIT = 253,
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R_MIPS_GNU_VTENTRY = 254
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};
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// Processor specific flags for the ELF header e_flags field.
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enum
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{
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// At least one .noreorder directive appears in the source.
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EF_MIPS_NOREORDER = 0x00000001,
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// File contains position independent code.
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EF_MIPS_PIC = 0x00000002,
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// Code in file uses the standard calling sequence for calling
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// position independent code.
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EF_MIPS_CPIC = 0x00000004,
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// ??? Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a.
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EF_MIPS_XGOT = 0x00000008,
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// Code in file uses UCODE (obsolete)
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EF_MIPS_UCODE = 0x00000010,
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// Code in file uses new ABI (-n32 on Irix 6).
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EF_MIPS_ABI2 = 0x00000020,
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// Process the .MIPS.options section first by ld
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EF_MIPS_OPTIONS_FIRST = 0x00000080,
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// Architectural Extensions used by this file
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EF_MIPS_ARCH_ASE = 0x0f000000,
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// Use MDMX multimedia extensions
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EF_MIPS_ARCH_ASE_MDMX = 0x08000000,
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// Use MIPS-16 ISA extensions
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EF_MIPS_ARCH_ASE_M16 = 0x04000000,
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// Use MICROMIPS ISA extensions.
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EF_MIPS_ARCH_ASE_MICROMIPS = 0x02000000,
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// Indicates code compiled for a 64-bit machine in 32-bit mode.
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// (regs are 32-bits wide.)
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EF_MIPS_32BITMODE = 0x00000100,
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// 32-bit machine but FP registers are 64 bit (-mfp64).
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EF_MIPS_FP64 = 0x00000200,
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/// Code in file uses the IEEE 754-2008 NaN encoding convention.
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EF_MIPS_NAN2008 = 0x00000400,
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// MIPS dynamic
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EF_MIPS_DYNAMIC = 0x40
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};
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// Machine variant if we know it. This field was invented at Cygnus,
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// but it is hoped that other vendors will adopt it. If some standard
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// is developed, this code should be changed to follow it.
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enum
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{
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EF_MIPS_MACH = 0x00FF0000,
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// Cygnus is choosing values between 80 and 9F;
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// 00 - 7F should be left for a future standard;
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// the rest are open.
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E_MIPS_MACH_3900 = 0x00810000,
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E_MIPS_MACH_4010 = 0x00820000,
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E_MIPS_MACH_4100 = 0x00830000,
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E_MIPS_MACH_4650 = 0x00850000,
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E_MIPS_MACH_4120 = 0x00870000,
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E_MIPS_MACH_4111 = 0x00880000,
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E_MIPS_MACH_SB1 = 0x008a0000,
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E_MIPS_MACH_OCTEON = 0x008b0000,
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E_MIPS_MACH_XLR = 0x008c0000,
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E_MIPS_MACH_OCTEON2 = 0x008d0000,
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E_MIPS_MACH_OCTEON3 = 0x008e0000,
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E_MIPS_MACH_5400 = 0x00910000,
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E_MIPS_MACH_5900 = 0x00920000,
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E_MIPS_MACH_5500 = 0x00980000,
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E_MIPS_MACH_9000 = 0x00990000,
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E_MIPS_MACH_LS2E = 0x00A00000,
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E_MIPS_MACH_LS2F = 0x00A10000,
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E_MIPS_MACH_GS464 = 0x00A20000,
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E_MIPS_MACH_GS464E = 0x00A30000,
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E_MIPS_MACH_GS264E = 0x00A40000,
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};
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// MIPS architecture
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enum
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{
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// Four bit MIPS architecture field.
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EF_MIPS_ARCH = 0xf0000000,
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// -mips1 code.
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E_MIPS_ARCH_1 = 0x00000000,
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// -mips2 code.
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E_MIPS_ARCH_2 = 0x10000000,
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// -mips3 code.
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E_MIPS_ARCH_3 = 0x20000000,
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// -mips4 code.
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E_MIPS_ARCH_4 = 0x30000000,
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// -mips5 code.
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E_MIPS_ARCH_5 = 0x40000000,
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// -mips32 code.
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E_MIPS_ARCH_32 = 0x50000000,
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// -mips64 code.
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E_MIPS_ARCH_64 = 0x60000000,
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// -mips32r2 code.
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E_MIPS_ARCH_32R2 = 0x70000000,
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// -mips64r2 code.
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E_MIPS_ARCH_64R2 = 0x80000000,
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// -mips32r6 code.
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E_MIPS_ARCH_32R6 = 0x90000000,
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// -mips64r6 code.
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E_MIPS_ARCH_64R6 = 0xa0000000,
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};
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// Values for the xxx_size bytes of an ABI flags structure.
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enum
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{
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// No registers.
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AFL_REG_NONE = 0x00,
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// 32-bit registers.
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AFL_REG_32 = 0x01,
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// 64-bit registers.
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AFL_REG_64 = 0x02,
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// 128-bit registers.
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AFL_REG_128 = 0x03
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};
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// Masks for the ases word of an ABI flags structure.
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enum
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{
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// DSP ASE.
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AFL_ASE_DSP = 0x00000001,
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// DSP R2 ASE.
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AFL_ASE_DSPR2 = 0x00000002,
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// Enhanced VA Scheme.
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AFL_ASE_EVA = 0x00000004,
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// MCU (MicroController) ASE.
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AFL_ASE_MCU = 0x00000008,
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// MDMX ASE.
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AFL_ASE_MDMX = 0x00000010,
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// MIPS-3D ASE.
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AFL_ASE_MIPS3D = 0x00000020,
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// MT ASE.
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AFL_ASE_MT = 0x00000040,
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// SmartMIPS ASE.
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AFL_ASE_SMARTMIPS = 0x00000080,
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// VZ ASE.
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AFL_ASE_VIRT = 0x00000100,
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// MSA ASE.
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AFL_ASE_MSA = 0x00000200,
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// MIPS16 ASE.
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AFL_ASE_MIPS16 = 0x00000400,
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// MICROMIPS ASE.
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AFL_ASE_MICROMIPS = 0x00000800,
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// XPA ASE.
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AFL_ASE_XPA = 0x00001000,
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// Loongson EXT ASE.
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AFL_ASE_LOONGSON_EXT = 0x00002000
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};
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// Values for the isa_ext word of an ABI flags structure.
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enum
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{
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// RMI Xlr instruction.
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AFL_EXT_XLR = 1,
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// Cavium Networks Octeon2.
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AFL_EXT_OCTEON2 = 2,
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// Cavium Networks OcteonP.
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AFL_EXT_OCTEONP = 3,
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// Loongson 3A.
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AFL_EXT_LOONGSON_3A = 4,
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// Cavium Networks Octeon.
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AFL_EXT_OCTEON = 5,
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// MIPS R5900 instruction.
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AFL_EXT_5900 = 6,
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// MIPS R4650 instruction.
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AFL_EXT_4650 = 7,
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// LSI R4010 instruction.
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AFL_EXT_4010 = 8,
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// NEC VR4100 instruction.
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AFL_EXT_4100 = 9,
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// Toshiba R3900 instruction.
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AFL_EXT_3900 = 10,
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// MIPS R10000 instruction.
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AFL_EXT_10000 = 11,
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// Broadcom SB-1 instruction.
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AFL_EXT_SB1 = 12,
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// NEC VR4111/VR4181 instruction.
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AFL_EXT_4111 = 13,
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// NEC VR4120 instruction.
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AFL_EXT_4120 = 14,
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// NEC VR5400 instruction.
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AFL_EXT_5400 = 15,
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// NEC VR5500 instruction.
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AFL_EXT_5500 = 16,
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// ST Microelectronics Loongson 2E.
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AFL_EXT_LOONGSON_2E = 17,
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// ST Microelectronics Loongson 2F.
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AFL_EXT_LOONGSON_2F = 18,
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// Cavium Networks Octeon3.
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AFL_EXT_OCTEON3 = 19
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};
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// Masks for the flags1 word of an ABI flags structure.
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enum
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{
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// Uses odd single-precision registers.
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AFL_FLAGS1_ODDSPREG = 1
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};
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// Object attribute tags.
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enum
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{
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// 0-3 are generic.
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// Floating-point ABI used by this object file.
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Tag_GNU_MIPS_ABI_FP = 4,
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// MSA ABI used by this object file.
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Tag_GNU_MIPS_ABI_MSA = 8
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};
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// Object attribute values.
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enum
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{
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// Values defined for Tag_GNU_MIPS_ABI_FP.
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// Not tagged or not using any ABIs affected by the differences.
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Val_GNU_MIPS_ABI_FP_ANY = 0,
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// Using hard-float -mdouble-float.
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Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
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// Using hard-float -msingle-float.
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Val_GNU_MIPS_ABI_FP_SINGLE = 2,
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// Using soft-float.
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Val_GNU_MIPS_ABI_FP_SOFT = 3,
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// Using -mips32r2 -mfp64.
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Val_GNU_MIPS_ABI_FP_OLD_64 = 4,
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// Using -mfpxx
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Val_GNU_MIPS_ABI_FP_XX = 5,
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// Using -mips32r2 -mfp64.
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Val_GNU_MIPS_ABI_FP_64 = 6,
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// Using -mips32r2 -mfp64 -mno-odd-spreg.
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Val_GNU_MIPS_ABI_FP_64A = 7,
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// This is reserved for backward-compatibility with an earlier
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// implementation of the MIPS NaN2008 functionality.
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Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
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// Values defined for Tag_GNU_MIPS_ABI_MSA.
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// Not tagged or not using any ABIs affected by the differences.
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Val_GNU_MIPS_ABI_MSA_ANY = 0,
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// Using 128-bit MSA.
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Val_GNU_MIPS_ABI_MSA_128 = 1
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};
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enum
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{
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// Mask to extract ABI version, not really a flag value.
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EF_MIPS_ABI = 0x0000F000,
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// The original o32 abi.
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E_MIPS_ABI_O32 = 0x00001000,
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// O32 extended to work on 64 bit architectures
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E_MIPS_ABI_O64 = 0x00002000,
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// EABI in 32 bit mode
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E_MIPS_ABI_EABI32 = 0x00003000,
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// EABI in 64 bit mode
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E_MIPS_ABI_EABI64 = 0x00004000,
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};
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// Dynamic section MIPS flags
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enum
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{
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// None
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RHF_NONE = 0x00000000,
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// Use shortcut pointers
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RHF_QUICKSTART = 0x00000001,
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// Hash size not power of two
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RHF_NOTPOT = 0x00000002,
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// Ignore LD_LIBRARY_PATH
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RHF_NO_LIBRARY_REPLACEMENT = 0x00000004
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};
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// Special values for the st_other field in the symbol table.
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enum
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{
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// Two topmost bits denote the MIPS ISA for .text symbols:
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// + 00 -- standard MIPS code,
|
|
// + 10 -- microMIPS code,
|
|
// + 11 -- MIPS16 code; requires the following two bits to be set too.
|
|
// Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC.
|
|
STO_MIPS_ISA = 0xc0,
|
|
|
|
// The mask spanning the rest of MIPS psABI flags. At most one is expected
|
|
// to be set except for STO_MIPS16.
|
|
STO_MIPS_FLAGS = ~(STO_MIPS_ISA | 0x3),
|
|
|
|
// The MIPS psABI was updated in 2008 with support for PLTs and copy
|
|
// relocs. There are therefore two types of nonzero SHN_UNDEF functions:
|
|
// PLT entries and traditional MIPS lazy binding stubs. We mark the former
|
|
// with STO_MIPS_PLT to distinguish them from the latter.
|
|
STO_MIPS_PLT = 0x8,
|
|
|
|
// This value is used to mark PIC functions in an object that mixes
|
|
// PIC and non-PIC. Note that this bit overlaps with STO_MIPS16,
|
|
// although MIPS16 symbols are never considered to be MIPS_PIC.
|
|
STO_MIPS_PIC = 0x20,
|
|
|
|
// This value is used for a mips16 .text symbol.
|
|
STO_MIPS16 = 0xf0,
|
|
|
|
// This value is used for a microMIPS .text symbol. To distinguish from
|
|
// STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS. The
|
|
// mask is STO_MIPS_ISA.
|
|
STO_MICROMIPS = 0x80
|
|
};
|
|
|
|
// Values for base offsets for thread-local storage
|
|
enum
|
|
{
|
|
TP_OFFSET = 0x7000,
|
|
DTP_OFFSET = 0x8000
|
|
};
|
|
|
|
|
|
bool
|
|
elf_st_is_mips16(unsigned char st_other)
|
|
{ return (st_other & elfcpp::STO_MIPS16) == elfcpp::STO_MIPS16; }
|
|
|
|
bool
|
|
elf_st_is_micromips(unsigned char st_other)
|
|
{ return (st_other & elfcpp::STO_MIPS_ISA) == elfcpp::STO_MICROMIPS; }
|
|
|
|
// Whether the ABI is N32.
|
|
bool
|
|
abi_n32(elfcpp::Elf_Word e_flags)
|
|
{ return (e_flags & elfcpp::EF_MIPS_ABI2) != 0; }
|
|
|
|
// Whether the ISA is R6.
|
|
bool
|
|
r6_isa(elfcpp::Elf_Word e_flags)
|
|
{
|
|
return ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32R6)
|
|
|| ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_64R6);
|
|
}
|
|
|
|
// Whether the file has microMIPS code.
|
|
bool
|
|
is_micromips(elfcpp::Elf_Word e_flags)
|
|
{ return (e_flags & elfcpp::EF_MIPS_ARCH_ASE_MICROMIPS) != 0; }
|
|
|
|
// Values which may appear in the kind field of an Elf_Options structure.
|
|
enum
|
|
{
|
|
// Undefined.
|
|
ODK_NULL = 0,
|
|
// Register usage and GP value.
|
|
ODK_REGINFO = 1,
|
|
// Exception processing information.
|
|
ODK_EXCEPTIONS = 2,
|
|
// Section padding information.
|
|
ODK_PAD = 3,
|
|
// Hardware workarounds performed.
|
|
ODK_HWPATCH = 4,
|
|
// Fill value used by the linker.
|
|
ODK_FILL = 5,
|
|
// Reserved space for desktop tools.
|
|
ODK_TAGS = 6,
|
|
// Hardware workarounds, AND bits when merging.
|
|
ODK_HWAND = 7,
|
|
// Hardware workarounds, OR bits when merging.
|
|
ODK_HWOR = 8,
|
|
// GP group to use for text/data sections.
|
|
ODK_GP_GROUP = 9,
|
|
// ID information.
|
|
ODK_IDENT = 10
|
|
};
|
|
|
|
} // End namespace elfcpp.
|
|
|
|
#endif // !defined(ELFCPP_MIPS_H)
|