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32c36c3ce9
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
364 lines
12 KiB
Plaintext
364 lines
12 KiB
Plaintext
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
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specifier. Add entries for VLDR and VSTR of system registers.
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(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
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coprocessor instructions on Armv8.1-M Mainline targets. Add handling
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of %J and %K format specifier.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
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Add new entries for VSCCLRM instruction.
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(print_insn_coprocessor): Handle new %C format control code.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (enum isa): New enum.
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(struct sopcode32): New structure.
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(coprocessor_opcodes): change type of entries to struct sopcode32 and
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set isa field of all current entries to ANY.
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(print_insn_coprocessor): Change type of insn to struct sopcode32.
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Only match an entry if its isa field allows the current mode.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
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CLRM.
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(print_insn_thumb32): Add logic to print %n CLRM register list.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %P
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and %Q patterns.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
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(print_insn_thumb32): Edit the switch case for %Z.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instruction bfl.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
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Arm register with r13 and r15 unpredictable.
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(thumb32_opcodes): New instructions for bfx and bflx.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instructions for bf.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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2019-04-12 John Darrington <john@darrington.wattle.id.au>
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s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
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"optr". ("operator" is a reserved word in c++).
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_print_operand): Add case for
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AARCH64_OPND_Rt_SP.
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(verify_constraints): Likewise.
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* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
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(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
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to accept Rt|SP as first operand.
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(AARCH64_OPERANDS): Add new Rt_SP.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-04-11 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
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2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
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* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Consolidate AVX512 BF16 entries.
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* i386-init.h: Regenerated.
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2019-04-07 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
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op_separator to control printing of spaces, comma and parens
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rather than need_comma, need_paren and spaces vars.
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2019-04-07 Alan Modra <amodra@gmail.com>
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PR 24421
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* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
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(print_insn_neon, print_insn_arm): Likewise.
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2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
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* i386-dis-evex.h (evex_table): Updated to support BF16
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instructions.
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* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
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and EVEX_W_0F3872_P_3.
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* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
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(cpu_flags): Add bitfield for CpuAVX512_BF16.
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* i386-opc.h (enum): Add CpuAVX512_BF16.
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(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
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* i386-opc.tbl: Add AVX512 BF16 instructions.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
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(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
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to favour printing of "-" branch hint when using the "y" bit.
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Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
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2019-04-05 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
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opcode until first operand is output.
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2019-04-04 Peter Bergner <bergner@linux.ibm.com>
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PR gas/24349
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* ppc-opc.c (valid_bo_pre_v2): Add comments.
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(valid_bo_post_v2): Add support for 'at' branch hints.
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(insert_bo): Only error on branch on ctr.
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(get_bo_hint_mask): New function.
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(insert_boe): Add new 'branch_taken' formal argument. Add support
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for inserting 'at' branch hints.
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(extract_boe): Add new 'branch_taken' formal argument. Add support
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for extracting 'at' branch hints.
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(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
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(BOE): Delete operand.
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(BOM, BOP): New operands.
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(RM): Update value.
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(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
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(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
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bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
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(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
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bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
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<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
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bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
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bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
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bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
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bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
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bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
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bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
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bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
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beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
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bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
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buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
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bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
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bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
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bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
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bttarl+>: New extended mnemonics.
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2019-03-28 Alan Modra <amodra@gmail.com>
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PR 24390
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* ppc-opc.c (BTF): Define.
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(powerpc_opcodes): Use for mtfsb*.
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* ppc-dis.c (print_insn_powerpc): Print fields with both
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PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
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(mapping_symbol_for_insn): Implement new algorithm.
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(print_insn): Remove duplicate code.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (print_insn_aarch64):
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Implement override.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
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order.
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2019-03-25 Tamar Christina <tamar.christina@arm.com>
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* aarch64-dis.c (last_stop_offset): New.
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(print_insn_aarch64): Use stop_offset.
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2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24359
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* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
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CPU_ANY_AVX2_FLAGS.
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* i386-init.h: Regenerated.
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2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24348
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* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
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vmovdqu16, vmovdqu32 and vmovdqu64.
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* i386-tbl.h: Regenerated.
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2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
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from vstrszb, vstrszh, and vstrszf.
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2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-opc.txt: Add instruction descriptions.
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2019-02-08 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
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<bne>: Likewise.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23212
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* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
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* aarch64-opc.c (verify_elem_sd): New.
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(fields): Add FLD_sz entr.
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* aarch64-tbl.h (_SIMD_INSN): New.
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(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
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fmulx scalar and vector by element isns.
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2019-02-07 Nick Clifton <nickc@redhat.com>
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* po/sv.po: Updated Swedish translation.
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2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
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* s390-mkopc.c (main): Accept arch13 as cpu string.
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* s390-opc.c: Add new instruction formats and instruction opcode
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masks.
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* s390-opc.txt: Add new arch13 instructions.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (QL_LDST_AT): Update macro.
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(aarch64_opcode): Change encoding for stg, stzg
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st2g and st2zg.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
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2019-01-25 Sudakshina Das <sudi.das@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
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* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
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* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
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* aarch64-dis.h (ext_addr_simple_2): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): Remove
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case for ldstgv_indexed.
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(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
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* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
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(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2019-01-23 Nick Clifton <nickc@redhat.com>
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* po/pt_BR.po: Updated Brazilian Portuguese translation.
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2019-01-21 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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* po/uk.po: Updated Ukranian translation.
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2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Fix typo in
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gs464, gs464e and gs264e descriptors.
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2019-01-19 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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* po/opcodes.pot: Regenerate.
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2018-06-24 Nick Clifton <nickc@redhat.com>
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2.32 branch created.
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2019-01-09 John Darrington <john@darrington.wattle.id.au>
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* s12z-dis.c (print_insn_s12z): Do not dereference an operand
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if it is null.
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-dis.c (opr_emit_disassembly): Do not omit an index if it is
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zero.
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2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
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* configure: Regenerate.
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2019-01-07 Alan Modra <amodra@gmail.com>
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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2019-01-03 John Darrington <john@darrington.wattle.id.au>
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* s12z-opc.c: New file.
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* s12z-opc.h: New file.
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* s12z-dis.c: Removed all code not directly related to display
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of instructions. Used the interface provided by the new files
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instead.
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* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
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* Makefile.in: Regenerate.
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* configure.ac (bfd_s12z_arch): Correct the dependencies.
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* configure: Regenerate.
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2019-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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For older changes see ChangeLog-2018
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|
||
Copyright (C) 2019 Free Software Foundation, Inc.
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|
||
Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
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|
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Local Variables:
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mode: change-log
|
||
left-margin: 8
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fill-column: 74
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version-control: never
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End:
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