mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
c1bd443b4d
This patch adds a target description and feature "mte" for aarch64. It includes one new register, tag_ctl, that can be used to configure the tag generation rules and sync/async modes. It is 64-bit in size. The patch also adjusts the code that creates the target descriptions at runtime based on CPU feature checks. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-nat.c (aarch64_linux_nat_target::read_description): Take MTE flag into account. Slight refactor to hwcap flag checking. * aarch64-linux-tdep.c (aarch64_linux_core_read_description): Likewise. * aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for MTE. (aarch64_read_description): Add mte_p parameter and update to use it. Update the documentation. (aarch64_gdbarch_init): Update call to aarch64_read_description. * aarch64-tdep.h (aarch64_read_description): Add mte_p parameter. * arch/aarch64.c: Include ../features/aarch64-mte.c. (aarch64_create_target_description): Add mte_p parameter and update the code to use it. * arch/aarch64.h (aarch64_create_target_description): Add mte_p parameter. * features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml. * features/aarch64-mte.c: New file, generated. * features/aarch64-mte.xml: New file. gdbserver/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to aarch64_linux_read_description. (initialize_low_tracepoint): Likewise. * linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag into account. * linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension for MTE. (aarch64_linux_read_description): Add mte_p parameter and update to use it. * linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p parameter.
111 lines
4.2 KiB
C
111 lines
4.2 KiB
C
/* Common target-dependent functionality for AArch64.
|
|
|
|
Copyright (C) 2017-2021 Free Software Foundation, Inc.
|
|
|
|
This file is part of GDB.
|
|
|
|
This program is free software; you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation; either version 3 of the License, or
|
|
(at your option) any later version.
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
|
|
|
#ifndef ARCH_AARCH64_H
|
|
#define ARCH_AARCH64_H
|
|
|
|
#include "gdbsupport/tdesc.h"
|
|
|
|
/* Create the aarch64 target description. A non zero VQ value indicates both
|
|
the presence of SVE and the Vector Quotient - the number of 128bit chunks in
|
|
an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH
|
|
feature.
|
|
|
|
MTE_P indicates the presence of the Memory Tagging Extension feature. */
|
|
|
|
target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p,
|
|
bool mte_p);
|
|
|
|
/* Register numbers of various important registers.
|
|
Note that on SVE, the Z registers reuse the V register numbers and the V
|
|
registers become pseudo registers. */
|
|
enum aarch64_regnum
|
|
{
|
|
AARCH64_X0_REGNUM, /* First integer register. */
|
|
AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */
|
|
AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
|
|
AARCH64_SP_REGNUM, /* Stack pointer. */
|
|
AARCH64_PC_REGNUM, /* Program counter. */
|
|
AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
|
|
AARCH64_V0_REGNUM, /* First fp/vec register. */
|
|
AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
|
|
AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
|
|
AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */
|
|
AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */
|
|
AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */
|
|
AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */
|
|
AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate
|
|
register. */
|
|
AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */
|
|
AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */
|
|
|
|
/* Other useful registers. */
|
|
AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
|
|
AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8,
|
|
AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
|
|
};
|
|
|
|
#define V_REGISTER_SIZE 16
|
|
|
|
/* Pseudo register base numbers. */
|
|
#define AARCH64_Q0_REGNUM 0
|
|
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
|
|
#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
|
|
#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
|
|
#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
|
|
#define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
|
|
|
|
#define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base)
|
|
#define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1)
|
|
#define AARCH64_PAUTH_REGS_SIZE (16)
|
|
|
|
#define AARCH64_X_REGS_NUM 31
|
|
#define AARCH64_V_REGS_NUM 32
|
|
#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM
|
|
#define AARCH64_SVE_P_REGS_NUM 16
|
|
#define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
|
|
#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
|
|
|
|
|
|
/* There are a number of ways of expressing the current SVE vector size:
|
|
|
|
VL : Vector Length.
|
|
The number of bytes in an SVE Z register.
|
|
VQ : Vector Quotient.
|
|
The number of 128bit chunks in an SVE Z register.
|
|
VG : Vector Granule.
|
|
The number of 64bit chunks in an SVE Z register. */
|
|
|
|
#define sve_vg_from_vl(vl) ((vl) / 8)
|
|
#define sve_vl_from_vg(vg) ((vg) * 8)
|
|
#ifndef sve_vq_from_vl
|
|
#define sve_vq_from_vl(vl) ((vl) / 0x10)
|
|
#endif
|
|
#ifndef sve_vl_from_vq
|
|
#define sve_vl_from_vq(vq) ((vq) * 0x10)
|
|
#endif
|
|
#define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
|
|
#define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
|
|
|
|
|
|
/* Maximum supported VQ value. Increase if required. */
|
|
#define AARCH64_MAX_SVE_VQ 16
|
|
|
|
#endif /* ARCH_AARCH64_H */
|