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https://sourceware.org/git/binutils-gdb.git
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807f647cac
Enable displaced stepping over a BR/BLR instruction
Displaced stepping over an instruction executes a instruction in a
scratch area and then manually fixes up the PC address to leave
execution where it would have been if the instruction were in its
original location.
The BR instruction does not need modification in order to run correctly
at a different address, but the displaced step fixup method should not
manually adjust the PC since the BR instruction sets that value already.
The BLR instruction should also avoid such a fixup, but must also have
the link register modified to point to just after the original code
location rather than back to the scratch location.
This patch adds the above functionality.
We add this functionality by modifying aarch64_displaced_step_others
rather than by adding a new visitor method to aarch64_insn_visitor.
We choose this since it seems that visitor approach is designed
specifically for PC relative instructions (which must always be modified
when executed in a different location).
It seems that the BR and BLR instructions are more like the RET
instruction which is already handled specially in
aarch64_displaced_step_others.
This also means the gdbserver code to relocate an instruction when
creating a fast tracepoint does not need to be modified, since nothing
special is needed for the BR and BLR instructions there.
Regression tests showed nothing untoward on native aarch64 (though it
took a while for me to get the testcase to account for PIE).
------#####
Original observed (mis)behaviour before was that displaced stepping over
a BR or BLR instruction would not execute the function they called.
Most easily seen by putting a breakpoint with a condition on such an
instruction and a print statement in the functions they called.
When run with the breakpoint enabled the function is not called and
"numargs called" is not printed.
When run with the breakpoint disabled the function is called and the
message is printed.
--- GDB Session
~ [15:57:14] % gdb ../using-blr
Reading symbols from ../using-blr...done.
(gdb) disassemble blr_call_value
Dump of assembler code for function blr_call_value:
...
0x0000000000400560 <+28>: blr x2
...
0x00000000004005b8 <+116>: ret
End of assembler dump.
(gdb) break *0x0000000000400560
Breakpoint 1 at 0x400560: file ../using-blr.c, line 22.
(gdb) condition 1 10 == 0
(gdb) run
Starting program: /home/matmal01/using-blr
[Inferior 1 (process 33279) exited with code 012]
(gdb) disable 1
(gdb) run
Starting program: /home/matmal01/using-blr
numargs called
[Inferior 1 (process 33289) exited with code 012]
(gdb)
Test program:
---- using-blr ----
\#include <stdio.h>
typedef int (foo) (int, int);
typedef void (bar) (int, int);
struct sls_testclass {
foo *x;
bar *y;
int left;
int right;
};
__attribute__ ((noinline))
int blr_call_value (struct sls_testclass x)
{
int retval = x.x(x.left, x.right);
if (retval % 10)
return 100;
return 9;
}
__attribute__ ((noinline))
int blr_call (struct sls_testclass x)
{
x.y(x.left, x.right);
if (x.left % 10)
return 100;
return 9;
}
int
numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("numargs called\n");
return 10;
}
void
altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("altfunc called\n");
}
int main(int argc, char **argv)
{
struct sls_testclass x = { .x = numargs, .y = altfunc, .left = 1, .right = 2 };
if (argc > 2)
{
blr_call (x);
}
else
blr_call_value (x);
return 10;
}
355 lines
12 KiB
C
355 lines
12 KiB
C
/* Copyright (C) 2009-2021 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef ARCH_AARCH64_INSN_H
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#define ARCH_AARCH64_INSN_H
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extern bool aarch64_debug;
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/* Print an "aarch64" debug statement. */
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#define aarch64_debug_printf(fmt, ...) \
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debug_prefixed_printf_cond (aarch64_debug, "aarch64", fmt, ##__VA_ARGS__)
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/* Support routines for instruction parsing. */
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/* Create a mask of X bits. */
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#define submask(x) ((1L << ((x) + 1)) - 1)
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/* Extract the bitfield from OBJ starting at bit ST and ending at bit FN. */
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#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
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/* Extract bit ST from OBJ. */
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#define bit(obj,st) (((obj) >> (st)) & 1)
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/* Extract the signed bitfield from OBJ starting at bit ST and ending at
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bit FN. The result is sign-extended. */
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#define sbits(obj,st,fn) \
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((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
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/* List of opcodes that we need for building the jump pad and relocating
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an instruction. */
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enum aarch64_opcodes
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{
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/* B 0001 01ii iiii iiii iiii iiii iiii iiii */
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/* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
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/* B.COND 0101 0100 iiii iiii iiii iiii iii0 cccc */
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/* CBZ s011 0100 iiii iiii iiii iiii iiir rrrr */
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/* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
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/* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
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/* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
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B = 0x14000000,
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BL = 0x80000000 | B,
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BCOND = 0x40000000 | B,
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CBZ = 0x20000000 | B,
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CBNZ = 0x21000000 | B,
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TBZ = 0x36000000 | B,
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TBNZ = 0x37000000 | B,
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/* BR 1101 0110 0001 1111 0000 00rr rrr0 0000 */
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/* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
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BR = 0xd61f0000,
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BLR = 0xd63f0000,
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/* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
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RET = 0xd65f0000,
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/* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
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/* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
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/* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
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/* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
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STP = 0x28000000,
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LDP = 0x28400000,
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STP_SIMD_VFP = 0x04000000 | STP,
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LDP_SIMD_VFP = 0x04000000 | LDP,
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/* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
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/* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
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/* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
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STR = 0x38000000,
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LDR = 0x00400000 | STR,
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LDRSW = 0x80800000 | STR,
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/* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
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LDAXR = 0x085ffc00,
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/* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
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STXR = 0x08007c00,
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/* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
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STLR = 0x089ffc00,
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/* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
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/* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
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MOV = 0x52800000,
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MOVK = 0x20000000 | MOV,
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/* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
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/* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
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/* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
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ADD = 0x01000000,
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SUB = 0x40000000 | ADD,
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SUBS = 0x20000000 | SUB,
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/* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
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/* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
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/* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
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/* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
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AND = 0x0a000000,
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ORR = 0x20000000 | AND,
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ORN = 0x00200000 | ORR,
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EOR = 0x40000000 | AND,
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/* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
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/* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
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/* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
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LSLV = 0x1ac02000,
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LSRV = 0x00000400 | LSLV,
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ASRV = 0x00000800 | LSLV,
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/* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
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SBFM = 0x13000000,
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/* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
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UBFM = 0x40000000 | SBFM,
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/* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
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CSINC = 0x9a800400,
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/* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
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MUL = 0x1b007c00,
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/* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
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/* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
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MSR = 0xd5100000,
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MRS = 0x00200000 | MSR,
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/* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
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HINT = 0xd503201f,
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SEVL = (5 << 5) | HINT,
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WFE = (2 << 5) | HINT,
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NOP = (0 << 5) | HINT,
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};
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/* List of useful masks. */
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enum aarch64_masks
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{
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/* Used for masking out an Rn argument from an opcode. */
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CLEAR_Rn_MASK = 0xfffffc1f,
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};
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/* Representation of a general purpose register of the form xN or wN.
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This type is used by emitting functions that take registers as operands. */
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struct aarch64_register
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{
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unsigned num;
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int is64;
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};
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enum aarch64_memory_operand_type
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{
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MEMORY_OPERAND_OFFSET,
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MEMORY_OPERAND_PREINDEX,
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MEMORY_OPERAND_POSTINDEX,
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};
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/* Representation of a memory operand, used for load and store
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instructions.
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The types correspond to the following variants:
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MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
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MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
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MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
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struct aarch64_memory_operand
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{
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/* Type of the operand. */
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enum aarch64_memory_operand_type type;
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/* Index from the base register. */
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int32_t index;
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};
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/* Helper macro to mask and shift a value into a bitfield. */
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#define ENCODE(val, size, offset) \
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((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
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int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
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unsigned *rd, int32_t *offset);
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int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
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int32_t *offset);
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int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
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int32_t *offset);
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int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
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int *is_cbnz, unsigned *rn, int32_t *offset);
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int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
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unsigned *bit, unsigned *rt, int32_t *imm);
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int aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
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int *is64, unsigned *rt, int32_t *offset);
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/* Data passed to each method of aarch64_insn_visitor. */
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struct aarch64_insn_data
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{
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/* The instruction address. */
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CORE_ADDR insn_addr;
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};
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/* Visit different instructions by different methods. */
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struct aarch64_insn_visitor
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{
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/* Visit instruction B/BL OFFSET. */
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void (*b) (const int is_bl, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction B.COND OFFSET. */
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void (*b_cond) (const unsigned cond, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction CBZ/CBNZ Rn, OFFSET. */
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void (*cb) (const int32_t offset, const int is_cbnz,
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const unsigned rn, int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET. */
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void (*tb) (const int32_t offset, int is_tbnz,
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const unsigned rt, unsigned bit,
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struct aarch64_insn_data *data);
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/* Visit instruction ADR/ADRP Rd, OFFSET. */
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void (*adr) (const int32_t offset, const unsigned rd,
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const int is_adrp, struct aarch64_insn_data *data);
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/* Visit instruction LDR/LDRSW Rt, OFFSET. */
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void (*ldr_literal) (const int32_t offset, const int is_sw,
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const unsigned rt, const int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction INSN of other kinds. */
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void (*others) (const uint32_t insn, struct aarch64_insn_data *data);
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};
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void aarch64_relocate_instruction (uint32_t insn,
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const struct aarch64_insn_visitor *visitor,
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struct aarch64_insn_data *data);
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#define can_encode_int32(val, bits) \
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(((val) >> (bits)) == 0 || ((val) >> (bits)) == -1)
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/* Write a B or BL instruction into *BUF.
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B #offset
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BL #offset
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IS_BL specifies if the link register should be updated.
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OFFSET is the immediate offset from the current PC. It is
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byte-addressed but should be 4 bytes aligned. It has a limited range of
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+/- 128MB (26 bits << 2). */
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#define emit_b(buf, is_bl, offset) \
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aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))
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/* Write a BCOND instruction into *BUF.
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B.COND #offset
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COND specifies the condition field.
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OFFSET is the immediate offset from the current PC. It is
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byte-addressed but should be 4 bytes aligned. It has a limited range of
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+/- 1MB (19 bits << 2). */
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#define emit_bcond(buf, cond, offset) \
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aarch64_emit_insn (buf, \
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BCOND | ENCODE ((offset) >> 2, 19, 5) \
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| ENCODE ((cond), 4, 0))
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/* Write a CBZ or CBNZ instruction into *BUF.
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CBZ rt, #offset
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CBNZ rt, #offset
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IS_CBNZ distinguishes between CBZ and CBNZ instructions.
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RN is the register to test.
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OFFSET is the immediate offset from the current PC. It is
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byte-addressed but should be 4 bytes aligned. It has a limited range of
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+/- 1MB (19 bits << 2). */
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#define emit_cb(buf, is_cbnz, rt, offset) \
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aarch64_emit_insn (buf, \
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((is_cbnz) ? CBNZ : CBZ) \
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| ENCODE (rt.is64, 1, 31) /* sf */ \
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| ENCODE (offset >> 2, 19, 5) /* imm19 */ \
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| ENCODE (rt.num, 5, 0))
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/* Write a LDR instruction into *BUF.
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LDR rt, [rn, #offset]
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LDR rt, [rn, #index]!
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LDR rt, [rn], #index
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RT is the register to store.
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RN is the base address register.
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OFFSET is the immediate to add to the base address. It is limited to
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0 .. 32760 range (12 bits << 3). */
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#define emit_ldr(buf, rt, rn, operand) \
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aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
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/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
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LDRSW xt, [rn, #offset]
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LDRSW xt, [rn, #index]!
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LDRSW xt, [rn], #index
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RT is the register to store.
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RN is the base address register.
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OFFSET is the immediate to add to the base address. It is limited to
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0 .. 16380 range (12 bits << 2). */
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#define emit_ldrsw(buf, rt, rn, operand) \
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aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
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/* Write a TBZ or TBNZ instruction into *BUF.
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TBZ rt, #bit, #offset
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TBNZ rt, #bit, #offset
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IS_TBNZ distinguishes between TBZ and TBNZ instructions.
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RT is the register to test.
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BIT is the index of the bit to test in register RT.
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OFFSET is the immediate offset from the current PC. It is
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byte-addressed but should be 4 bytes aligned. It has a limited range of
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+/- 32KB (14 bits << 2). */
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#define emit_tb(buf, is_tbnz, bit, rt, offset) \
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aarch64_emit_insn (buf, \
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((is_tbnz) ? TBNZ: TBZ) \
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| ENCODE (bit >> 5, 1, 31) /* b5 */ \
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| ENCODE (bit, 5, 19) /* b40 */ \
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| ENCODE (offset >> 2, 14, 5) /* imm14 */ \
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| ENCODE (rt.num, 5, 0))
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/* Write a NOP instruction into *BUF. */
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#define emit_nop(buf) aarch64_emit_insn (buf, NOP)
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int aarch64_emit_insn (uint32_t *buf, uint32_t insn);
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int aarch64_emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand);
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#endif /* ARCH_AARCH64_INSN_H */
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