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RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
163 lines
5.2 KiB
C
163 lines
5.2 KiB
C
/* tc-riscv.h -- header file for tc-riscv.c.
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Copyright (C) 2011-2022 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (andrew@sifive.com).
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Based on MIPS target.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef TC_RISCV
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#define TC_RISCV
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#include "opcode/riscv.h"
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struct frag;
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struct expressionS;
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#ifndef TARGET_BYTES_BIG_ENDIAN
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#define TARGET_BYTES_BIG_ENDIAN 0
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#endif
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#define TARGET_ARCH bfd_arch_riscv
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#define WORKING_DOT_WORD 1
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#define LOCAL_LABELS_FB 1
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/* Symbols named FAKE_LABEL_NAME are emitted when generating DWARF, so make
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sure FAKE_LABEL_NAME is printable. It still must be distinct from any
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real label name. So, append a space, which other labels can't contain. */
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#define FAKE_LABEL_NAME RISCV_FAKE_LABEL_NAME
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/* Changing the special character in FAKE_LABEL_NAME requires changing
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FAKE_LABEL_CHAR too. */
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#define FAKE_LABEL_CHAR RISCV_FAKE_LABEL_CHAR
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#define md_relax_frag(segment, fragp, stretch) \
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riscv_relax_frag (segment, fragp, stretch)
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extern int riscv_relax_frag (asection *, struct frag *, long);
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#define md_section_align(seg,size) (size)
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#define md_undefined_symbol(name) (0)
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#define md_operand(x)
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extern bool riscv_frag_align_code (int);
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#define md_do_align(N, FILL, LEN, MAX, LABEL) \
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if ((N) != 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg)) \
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{ \
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if (riscv_frag_align_code (N)) \
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goto LABEL; \
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}
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extern void riscv_handle_align (fragS *);
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#define HANDLE_ALIGN riscv_handle_align
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#define MAX_MEM_FOR_RS_ALIGN_CODE (3 + 4)
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/* The ISA of the target may change based on command-line arguments. */
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#define TARGET_FORMAT riscv_target_format ()
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extern const char * riscv_target_format (void);
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#define md_after_parse_args() riscv_after_parse_args ()
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extern void riscv_after_parse_args (void);
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#define md_parse_long_option(arg) riscv_parse_long_option (arg)
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extern int riscv_parse_long_option (const char *);
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#define md_pre_output_hook riscv_pre_output_hook ()
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extern void riscv_pre_output_hook (void);
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#define GAS_SORT_RELOCS 1
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/* Let the linker resolve all the relocs due to relaxation. */
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#define tc_fix_adjustable(fixp) 0
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#define md_allow_local_subtract(l,r,s) 0
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/* Values passed to md_apply_fix don't include symbol values. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
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/* Global syms must not be resolved, to support ELF shared libraries. */
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#define EXTERN_FORCE_RELOC \
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(OUTPUT_FLAVOR == bfd_target_elf_flavour)
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/* Postpone text-section label subtraction calculation until linking, since
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linker relaxations might change the deltas. */
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#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \
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(GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEG) \
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|| ((SEG)->flags & SEC_CODE) != 0)
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#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1
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#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1
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#define TC_FORCE_RELOCATION_LOCAL(FIX) 1
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#define DIFF_EXPR_OK 1
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extern void riscv_pop_insert (void);
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#define md_pop_insert() riscv_pop_insert ()
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#define TARGET_USE_CFIPOP 1
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#define tc_cfi_frame_initial_instructions riscv_cfi_frame_initial_instructions
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extern void riscv_cfi_frame_initial_instructions (void);
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#define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum
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extern int tc_riscv_regname_to_dw2regnum (char *);
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#define DWARF2_DEFAULT_RETURN_COLUMN X_RA
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/* Even on RV64, use 4-byte alignment, as F registers may be only 32 bits. */
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#define DWARF2_CIE_DATA_ALIGNMENT -4
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#define elf_tc_final_processing riscv_elf_final_processing
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extern void riscv_elf_final_processing (void);
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/* Adjust debug_line after relaxation. */
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#define DWARF2_USE_FIXED_ADVANCE_PC 1
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#define md_finish riscv_md_finish
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#define CONVERT_SYMBOLIC_ATTRIBUTE riscv_convert_symbolic_attribute
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extern void riscv_md_finish (void);
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extern int riscv_convert_symbolic_attribute (const char *);
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/* Set mapping symbol states. */
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#define md_cons_align(nbytes) riscv_mapping_state (MAP_DATA, 0, 0)
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void riscv_mapping_state (enum riscv_seg_mstate, int, bool);
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/* Define target segment type. */
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#define TC_SEGMENT_INFO_TYPE struct riscv_segment_info_type
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struct riscv_segment_info_type
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{
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enum riscv_seg_mstate map_state;
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/* The current mapping symbol with architecture string. */
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symbolS *arch_map_symbol;
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};
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/* Define target fragment type. */
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#define TC_FRAG_TYPE struct riscv_frag_type
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struct riscv_frag_type
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{
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symbolS *first_map_symbol, *last_map_symbol;
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};
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#define TC_FRAG_INIT(fragp, max_bytes) riscv_init_frag (fragp, max_bytes)
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extern void riscv_init_frag (struct frag *, int);
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#define obj_adjust_symtab() riscv_adjust_symtab ()
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extern void riscv_adjust_symtab (void);
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void riscv_elf_copy_symbol_attributes (symbolS *, symbolS *);
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#define OBJ_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
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riscv_elf_copy_symbol_attributes (DEST, SRC)
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#endif /* TC_RISCV */
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