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c2b1c27545
When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
69 lines
2.3 KiB
Makefile
69 lines
2.3 KiB
Makefile
#source: tlsopt5.s
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#as: -a64
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#ld: -shared --gc-sections --no-plt-localentry tlsdll.so
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#objdump: -dr
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#target: powerpc64*-*-*
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.*
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Disassembly of section \.text:
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.* <.*\.plt_call\.foo>:
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (28 80 82 e9|e9 82 80 28) ld r12,-32728\(r2\)
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (20 04 80 4e|4e 80 04 20) bctr
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\.\.\.
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.* <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>:
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.*: (00 00 63 e9|e9 63 00 00) ld r11,0\(r3\)
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.*: (08 00 83 e9|e9 83 00 08) ld r12,8\(r3\)
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.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3
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.*: (00 00 2b 2c|2c 2b 00 00) cmpdi r11,0
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.*: (14 6a 6c 7c|7c 6c 6a 14) add r3,r12,r13
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.*: (20 00 82 4d|4d 82 00 20) beqlr
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.*: (78 03 03 7c|7c 03 03 78) mr r3,r0
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (08 00 61 f9|f9 61 00 08) std r11,8\(r1\)
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (30 80 82 e9|e9 82 80 30) ld r12,-32720\(r2\)
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (21 04 80 4e|4e 80 04 21) bctrl
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (08 00 61 e9|e9 61 00 08) ld r11,8\(r1\)
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.*: (a6 03 68 7d|7d 68 03 a6) mtlr r11
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.*: (20 00 80 4e|4e 80 00 20) blr
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\.\.\.
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.* <_start>:
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.*: (08 80 62 38|38 62 80 08) addi r3,r2,-32760
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.*: (9d ff ff 4b|4b ff ff 9d) bl .* <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (75 ff ff 4b|4b ff ff 75) bl .* <.*\.plt_call\.foo>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (00 00 00 60|60 00 00 00) nop
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.*
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.*
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.* <__glink_PLTresolve>:
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.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\)
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.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
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.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12
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.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11
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.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48
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.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
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.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\)
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.*: (20 04 80 4e|4e 80 04 20) bctr
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.* <foo@plt>:
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.* (c8 ff ff 4b|4b ff ff c8) b .*
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.* <__tls_get_addr_opt@plt>:
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.*: (c4 ff ff 4b|4b ff ff c4) b .*
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