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c2b1c27545
When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
76 lines
3.0 KiB
Makefile
76 lines
3.0 KiB
Makefile
#source: tls32.s
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#as: -a32
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#ld: tmpdir/libtlslib32.so
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#objdump: -dr
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#target: powerpc*-*-*
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.*
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Disassembly of section \.text:
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.* <_start>:
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.*: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.* <_start\+0x4>
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.*: (7f c8 02 a6|a6 02 c8 7f) mflr r30
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.*: (3f de 00 02|02 00 de 3f) addis r30,r30,2
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.*: (3b de 81 08|08 81 de 3b) addi r30,r30,-32504
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.*: (80 7f ff f4|f4 ff 7f 80) lwz r3,-12\(r31\)
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.*: (7c 63 12 14|14 12 63 7c) add r3,r3,r2
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.*: (38 7f ff f8|f8 ff 7f 38) addi r3,r31,-8
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.*: (48 00 00 65|65 00 00 48) bl .* <__tls_get_addr_opt@plt>
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.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
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.*: (38 63 90 1c|1c 90 63 38) addi r3,r3,-28644
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.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (39 23 80 20|20 80 23 39) addi r9,r3,-32736
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (81 49 80 24|24 80 49 81) lwz r10,-32732\(r9\)
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.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
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.*: (a1 49 90 2c|2c 90 49 a1) lhz r10,-28628\(r9\)
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.*: (89 42 90 30|30 90 42 89) lbz r10,-28624\(r2\)
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.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
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.*: (99 49 90 34|34 90 49 99) stb r10,-28620\(r9\)
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.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
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.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
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.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\)
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\)
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.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
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.*: (b1 49 90 2c|2c 90 49 b1) sth r10,-28628\(r9\)
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.*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\)
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.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
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.*: (a9 49 90 18|18 90 49 a9) lha r10,-28648\(r9\)
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.* <__tls_get_addr_opt@plt>:
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.*: (81 63 00 00|00 00 63 81) lwz r11,0\(r3\)
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.*: (81 83 00 04|04 00 83 81) lwz r12,4\(r3\)
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.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
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.*: (2c 0b 00 00|00 00 0b 2c) cmpwi r11,0
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.*: (7c 6c 12 14|14 12 6c 7c) add r3,r12,r2
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.*: (4d 82 00 20|20 00 82 4d) beqlr
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.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3d 60 01 81|81 01 60 3d) lis r11,385
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.*: (81 6b 03 94|94 03 6b 81) lwz r11,916\(r11\)
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.*: (7d 69 03 a6|a6 03 69 7d) mtctr r11
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <__glink(_PLTresolve)?>:
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.*: (3d 80 01 81|81 01 80 3d) lis r12,385
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.*: (3d 6b fe 80|80 fe 6b 3d) addis r11,r11,-384
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.*: (80 0c 03 8c|8c 03 0c 80) lwz r0,908\(r12\)
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.*: (39 6b fd 90|90 fd 6b 39) addi r11,r11,-624
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.*: (7c 09 03 a6|a6 03 09 7c) mtctr r0
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.*: (7c 0b 5a 14|14 5a 0b 7c) add r0,r11,r11
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.*: (81 8c 03 90|90 03 8c 81) lwz r12,912\(r12\)
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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