Cooper Qu 9d1ccf22fd CSKY: Add version flag in eflag and fix bug in disassembling register. ... gas/ * config/tc-csky.c (md_begin): Add version flag in eflag. include/ * opcode/csky.h (CSKY_VERSION_V1): Define, currently used. (CSKY_VERSION_V2): Define. (CSKY_VERSION_V3): Define. Change-Id: Iafe3a9ce6fe544880a225b9fae439275a828bb34		2020-10-26 16:20:10 +08:00
..
aarch64.h	aarch64: Add support for Armv8-R system registers	2020-09-08 14:21:44 +01:00
alpha.h
arc-attrs.h
arc-func.h
arc.h
arm.h
avr.h
bfin.h
cgen.h	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
csky.h	CSKY: Add version flag in eflag and fix bug in disassembling register.	2020-10-26 16:20:10 +08:00
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h
ia64.h
m68hc11.h
m68k.h
metag.h
mips.h
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h
pru.h
pyr.h
riscv-opc.h	RISC-V: Support debug and float CSR as the unprivileged ones.	2020-06-30 09:54:55 +08:00
riscv.h	PR26493 UBSAN: elfnn-riscv.c left shift of negative value	2020-08-31 20:28:10 +09:30
rl78.h
rx.h
s12z.h
s390.h
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tilegx.h
tilepro.h
v850.h	ubsan: v850-opc.c:412 left shift cannot be represented	2020-09-02 16:30:44 +09:30
vax.h
visium.h
wasm.h
xgate.h