binutils-gdb/sim/example-synacor
Mike Frysinger c0c25232da sim: run: move linking into top-level
Automake will run each subdir individually before moving on to the next
one.  This means that the linking phase, a single threaded process, will
not run in parallel with anything else.  When we have to link ~32 ports,
that's 32 link steps that don't take advantage of parallel systems.  On
my really old 4-core system, this cuts a multi-target build from ~60 sec
to ~30 sec.  We eventually want to move all compile+link steps to this
common dir anyways, so might as well move linking now for a nice speedup.

We use noinst_PROGRAMS instead of bin_PROGRAMS because we're taking care
of the install ourselves rather than letting automake process it.
2022-11-05 20:00:56 +07:00
..
ChangeLog-2021
interp.c Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00
local.mk sim: run: move linking into top-level 2022-11-05 20:00:56 +07:00
Makefile.in Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00
README
README.arch-spec
sim-main.c sim: synacor: migrate to standard uintXX_t types 2022-01-06 01:17:38 -05:00
sim-main.h sim: synacor: migrate to standard uintXX_t types 2022-01-06 01:17:38 -05:00

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.