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8fdffbc4b3
function up into several smaller ones and arranged for
the instruction printing function to be callable recursively
to print vector instructions that have both a load and a
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
473 lines
14 KiB
C
473 lines
14 KiB
C
/* Print TI TMS320C80 (MVP) instructions
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Copyright 1996, 1997 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "ansidecl.h"
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#include "opcode/tic80.h"
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#include "dis-asm.h"
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static int length;
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static void print_operand_bitnum PARAMS ((struct disassemble_info *, long));
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static void print_operand_condition_code PARAMS ((struct disassemble_info *, long));
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static void print_operand_control_register PARAMS ((struct disassemble_info *, long));
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static void print_operand_float PARAMS ((struct disassemble_info *, long));
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static void print_operand_integer PARAMS ((struct disassemble_info *, long));
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static void print_operand PARAMS ((struct disassemble_info *, long, unsigned long,
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const struct tic80_operand *, bfd_vma));
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static int print_one_instruction PARAMS ((struct disassemble_info *, bfd_vma,
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unsigned long, const struct tic80_opcode *));
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static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long,
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const struct tic80_opcode *));
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static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma,
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unsigned long *));
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/* Print an integer operand. Try to be somewhat smart about the
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format by assuming that small positive or negative integers are
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probably loop increment values, structure offsets, or similar
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values that are more meaningful printed as signed decimal values.
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Larger numbers are probably better printed as hex values. */
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static void
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print_operand_integer (info, value)
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struct disassemble_info *info;
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long value;
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{
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if ((value > 9999 || value < -9999))
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{
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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else
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{
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(*info -> fprintf_func) (info -> stream, "%ld", value);
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}
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}
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/* FIXME: depends upon sizeof (long) == sizeof (float) and
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also upon host floating point format matching target
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floating point format. */
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static void
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print_operand_float (info, value)
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struct disassemble_info *info;
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long value;
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{
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union { float f; long l; } fval;
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fval.l = value;
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(*info -> fprintf_func) (info -> stream, "%g", fval.f);
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}
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static void
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print_operand_control_register (info, value)
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struct disassemble_info *info;
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long value;
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{
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char *tmp;
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switch (value)
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{
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case 0: tmp = "EPC"; break;
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case 1: tmp = "EIP"; break;
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case 2: tmp = "CONFIG"; break;
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case 4: tmp = "INTPEN"; break;
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case 6: tmp = "IE"; break;
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case 8: tmp = "FPST"; break;
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case 0xA: tmp = "PPERROR"; break;
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case 0xD: tmp = "PKTREQ"; break;
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case 0xE: tmp = "TCOUNT"; break;
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case 0xF: tmp = "TSCALE"; break;
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case 0x10: tmp = "FLTOP"; break;
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case 0x11: tmp = "FLTADR"; break;
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case 0x12: tmp = "FLTTAG"; break;
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case 0x13: tmp = "FLTDTL"; break;
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case 0x14: tmp = "FLTDTH"; break;
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case 0x20: tmp = "SYSSTK"; break;
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case 0x21: tmp = "SYSTMP"; break;
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case 0x30: tmp = "MPC"; break;
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case 0x31: tmp = "MIP"; break;
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case 0x33: tmp = "ECOMCNTL"; break;
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case 0x34: tmp = "ANASTAT"; break;
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case 0x39: tmp = "BRK1"; break;
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case 0x3A: tmp = "BRK2"; break;
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case 0x200: tmp = "ITAG0"; break;
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case 0x201: tmp = "ITAG1"; break;
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case 0x202: tmp = "ITAG2"; break;
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case 0x203: tmp = "ITAG3"; break;
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case 0x204: tmp = "ITAG4"; break;
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case 0x205: tmp = "ITAG5"; break;
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case 0x206: tmp = "ITAG6"; break;
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case 0x207: tmp = "ITAG7"; break;
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case 0x208: tmp = "ITAG8"; break;
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case 0x209: tmp = "ITAG9"; break;
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case 0x20A: tmp = "ITAG10"; break;
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case 0x20B: tmp = "ITAG11"; break;
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case 0x20C: tmp = "ITAG12"; break;
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case 0x20D: tmp = "ITAG13"; break;
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case 0x20E: tmp = "ITAG14"; break;
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case 0x20F: tmp = "ITAG15"; break;
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case 0x300: tmp = "ILRU"; break;
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case 0x400: tmp = "DTAG0"; break;
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case 0x401: tmp = "DTAG1"; break;
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case 0x402: tmp = "DTAG2"; break;
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case 0x403: tmp = "DTAG3"; break;
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case 0x404: tmp = "DTAG4"; break;
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case 0x405: tmp = "DTAG5"; break;
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case 0x406: tmp = "DTAG6"; break;
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case 0x407: tmp = "DTAG7"; break;
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case 0x408: tmp = "DTAG8"; break;
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case 0x409: tmp = "DTAG9"; break;
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case 0x40A: tmp = "DTAG10"; break;
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case 0x40B: tmp = "DTAG11"; break;
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case 0x40C: tmp = "DTAG12"; break;
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case 0x40D: tmp = "DTAG13"; break;
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case 0x40E: tmp = "DTAG14"; break;
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case 0x40F: tmp = "DTAG15"; break;
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case 0x500: tmp = "DLRU"; break;
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case 0x4000: tmp = "IN0P"; break;
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case 0x4001: tmp = "IN1P"; break;
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case 0x4002: tmp = "OUTP"; break;
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default: tmp = NULL; break;
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}
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if (tmp != NULL)
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{
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(*info -> fprintf_func) (info -> stream, "%s", tmp);
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}
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else
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{
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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}
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static void
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print_operand_condition_code (info, value)
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struct disassemble_info *info;
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long value;
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{
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const char *syms[] = {
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"nev.b", "gt0.b", "eq0.b", "ge0.b", "lt0.b", "ne0.b", "le0.b", "alw.b",
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"nev.h", "gt0.h", "eq0.h", "ge0.h", "lt0.h", "ne0.h", "le0.h", "alw.h",
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"nev.w", "gt0.w", "eq0.w", "ge0.w", "lt0.w", "ne0.w", "le0.w", "alw.w"
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};
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if (value < (sizeof (syms) / sizeof (syms[0])))
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{
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/* Found a value within range */
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(*info -> fprintf_func) (info -> stream, "%s", syms[value]);
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}
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else
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{
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/* Not in range, just print as decimal digit. */
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(*info -> fprintf_func) (info -> stream, "%ld", value);
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}
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}
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static void
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print_operand_bitnum (info, value)
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struct disassemble_info *info;
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long value;
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{
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int bitnum;
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const char *syms[] = {
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"eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b",
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"hi.b", "ls.b", "lo.b", "hs.b", "eq.h", "ne.h",
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"gt.h", "le.h", "lt.h", "ge.h", "hi.h", "ls.h",
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"lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w",
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"lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w"
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};
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bitnum = ~value & 0x1F;
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if (bitnum < (sizeof (syms) / sizeof (syms[0])))
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{
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/* Found a value within range */
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(*info -> fprintf_func) (info -> stream, "%s", syms[bitnum]);
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}
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else
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{
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/* Not in range, just print as bit number */
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(*info -> fprintf_func) (info -> stream, "%ld", bitnum);
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}
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}
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/* Print the operand as directed by the flags. */
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#define M_SI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17)))
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#define M_LI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15)))
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#define R_SCALED(insn,op) ((((op) -> flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11)))
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static void
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print_operand (info, value, insn, operand, memaddr)
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struct disassemble_info *info;
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long value;
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unsigned long insn;
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const struct tic80_operand *operand;
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bfd_vma memaddr;
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{
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if ((operand -> flags & TIC80_OPERAND_GPR) != 0)
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{
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(*info -> fprintf_func) (info -> stream, "r%ld", value);
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if (M_SI (insn, operand) || M_LI (insn, operand))
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{
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(*info -> fprintf_func) (info -> stream, ":m");
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}
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}
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else if ((operand -> flags & TIC80_OPERAND_FPA) != 0)
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{
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(*info -> fprintf_func) (info -> stream, "a%ld", value);
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}
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else if ((operand -> flags & TIC80_OPERAND_PCREL) != 0)
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{
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(*info -> print_address_func) (memaddr + 4 * value, info);
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}
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else if ((operand -> flags & TIC80_OPERAND_BASEREL) != 0)
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{
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(*info -> print_address_func) (value, info);
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}
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else if ((operand -> flags & TIC80_OPERAND_BITNUM) != 0)
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{
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print_operand_bitnum (info, value);
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}
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else if ((operand -> flags & TIC80_OPERAND_CC) != 0)
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{
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print_operand_condition_code (info, value);
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}
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else if ((operand -> flags & TIC80_OPERAND_CR) != 0)
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{
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print_operand_control_register (info, value);
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}
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else if ((operand -> flags & TIC80_OPERAND_FLOAT) != 0)
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{
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print_operand_float (info, value);
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}
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else if ((operand -> flags & TIC80_OPERAND_BITFIELD))
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{
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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else
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{
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print_operand_integer (info, value);
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}
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/* If this is a scaled operand, then print the modifier */
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if (R_SCALED (insn, operand))
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{
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(*info -> fprintf_func) (info -> stream, ":s");
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}
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}
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/* We have chosen an opcode table entry */
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static int
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print_one_instruction (info, memaddr, insn, opcode)
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struct disassemble_info *info;
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bfd_vma memaddr;
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unsigned long insn;
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const struct tic80_opcode *opcode;
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{
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const struct tic80_operand *operand;
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long value;
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int status;
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const unsigned char *opindex;
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bfd_byte buffer[4];
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int close_paren;
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(*info -> fprintf_func) (info -> stream, "%-10s", opcode -> name);
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for (opindex = opcode -> operands; *opindex != 0; opindex++)
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{
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operand = tic80_operands + *opindex;
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/* Extract the value from the instruction. */
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if (operand -> extract)
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{
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value = (*operand -> extract) (insn, (int *) NULL);
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}
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else if (operand -> bits == 32)
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{
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status = fill_instruction (info, memaddr, (unsigned long *) &value);
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if (status == -1)
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{
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return (status);
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}
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}
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else
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{
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value = (insn >> operand -> shift) & ((1 << operand -> bits) - 1);
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if ((operand -> flags & TIC80_OPERAND_SIGNED) != 0
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&& (value & (1 << (operand -> bits - 1))) != 0)
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{
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value -= 1 << operand -> bits;
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}
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}
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/* If this operand is enclosed in parenthesis, then print
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the open paren, otherwise just print the regular comma
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separator, except for the first operand. */
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if ((operand -> flags & TIC80_OPERAND_PARENS) == 0)
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{
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close_paren = 0;
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if (opindex != opcode -> operands)
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{
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(*info -> fprintf_func) (info -> stream, ",");
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}
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}
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else
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{
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close_paren = 1;
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(*info -> fprintf_func) (info -> stream, "(");
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}
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print_operand (info, value, insn, operand, memaddr);
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/* If we printed an open paren before printing this operand, close
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it now. The flag gets reset on each loop. */
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if (close_paren)
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{
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(*info -> fprintf_func) (info -> stream, ")");
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}
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}
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return (length);
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}
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/* There are no specific bits that tell us for certain whether a vector
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instruction opcode contains one or two instructions. However since
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a destination register of r0 is illegal, we can check for nonzero
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values in both destination register fields. Only opcodes that have
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two valid instructions will have non-zero in both */
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#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0))
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static int
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print_instruction (info, memaddr, insn, vec_opcode)
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struct disassemble_info *info;
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bfd_vma memaddr;
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unsigned long insn;
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const struct tic80_opcode *vec_opcode;
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{
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const struct tic80_opcode *opcode;
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const struct tic80_opcode *opcode_end;
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/* Find the first opcode match in the opcodes table. For vector
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opcodes (vec_opcode != NULL) find the first match that is not the
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previously found match. FIXME: there should be faster ways to
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search (hash table or binary search), but don't worry too much
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about it until other TIc80 support is finished. */
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opcode_end = tic80_opcodes + tic80_num_opcodes;
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for (opcode = tic80_opcodes; opcode < opcode_end; opcode++)
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{
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if ((insn & opcode -> mask) == opcode -> opcode &&
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opcode != vec_opcode)
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{
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break;
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}
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}
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if (opcode == opcode_end)
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{
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/* No match found, just print the bits as a .word directive */
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(*info -> fprintf_func) (info -> stream, ".word %#08lx", insn);
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}
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else
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{
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/* Match found, decode the instruction. */
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length = print_one_instruction (info, memaddr, insn, opcode);
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if (opcode -> flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn))
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{
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/* There is another instruction to print from the same opcode.
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Print the separator and then find and print the other
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instruction. */
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(*info -> fprintf_func) (info -> stream, " || ");
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length = print_instruction (info, memaddr, insn, opcode);
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}
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}
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return (length);
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}
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/* Get the next 32 bit word from the instruction stream and convert it
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into internal format in the unsigned long INSN, for which we are
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passed the address. Return 0 on success, -1 on error. */
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static int
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fill_instruction (info, memaddr, insnp)
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struct disassemble_info *info;
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bfd_vma memaddr;
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unsigned long *insnp;
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{
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bfd_byte buffer[4];
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int status;
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/* Get the bits for the next 32 bit word and put in buffer */
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status = (*info -> read_memory_func) (memaddr + length, buffer, 4, info);
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if (status != 0)
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{
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(*info -> memory_error_func) (status, memaddr, info);
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return (-1);
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}
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/* Read was successful, so increment count of bytes read and convert
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the bits into internal format. */
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length += 4;
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if (info -> endian == BFD_ENDIAN_LITTLE)
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{
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*insnp = bfd_getl32 (buffer);
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}
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else if (info -> endian == BFD_ENDIAN_BIG)
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{
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*insnp = bfd_getb32 (buffer);
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}
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else
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{
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/* FIXME: Should probably just default to one or the other */
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abort ();
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}
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return (0);
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}
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int
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print_insn_tic80 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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unsigned long insn;
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int status;
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length = 0;
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status = fill_instruction (info, memaddr, &insn);
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if (status != -1)
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{
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status = print_instruction (info, memaddr, insn, NULL);
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}
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return (status);
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}
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