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e70cb6cd9a
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
258 lines
5.9 KiB
C
258 lines
5.9 KiB
C
// -*- C -*-
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//
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// NEC specific instructions
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//
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:%s::::MFHI:int hi
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{
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return hi ? "hi" : "";
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}
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:%s::::SAT:int s
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{
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return s ? "s" : "";
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}
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:%s::::UNS:int u
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{
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return u ? "u" : "";
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}
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// Simulate the various kinds of multiply and multiply-accumulate instructions.
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// Perform an operation of the form:
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//
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// LHS (+/-) GPR[RS] * GPR[RT]
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//
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// and store it in the 64-bit accumulator. Optionally copy either LO or
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// HI into a general purpose register.
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//
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// - RD is the destination register of the LO or HI move
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// - RS are RT are the multiplication source registers
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// - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
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// false if it should be 0.
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// - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
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// - UNSIGNED_P is true if the operation should be unsigned.
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// - SATURATE_P is true if the result should be saturated to a 32-bit value.
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// - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
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// false if it should be added.
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// - SHORT_P is true if RS and RT must be 16-bit numbers.
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// - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
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// concatenation of the low 32 bits of HI and LO.
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:function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
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{
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unsigned64 lhs, x, y, xcut, ycut, product, result;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
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x = GPR[rs];
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y = GPR[rt];
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/* Work out the canonical form of X and Y from their significant bits. */
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if (!short_p)
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{
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/* Normal sign-extension rule for 32-bit operands. */
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xcut = EXTEND32 (x);
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ycut = EXTEND32 (y);
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}
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else if (unsigned_p)
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{
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/* Operands must be zero-extended 16-bit numbers. */
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xcut = x & 0xffff;
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ycut = y & 0xffff;
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}
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else
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{
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/* Likewise but sign-extended. */
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xcut = EXTEND16 (x);
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ycut = EXTEND16 (y);
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}
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if (x != xcut || y != ycut)
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sim_engine_abort (SD, CPU, CIA,
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"invalid multiplication operand at 0x%08lx\n",
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(long) CIA);
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TRACE_ALU_INPUT2 (x, y);
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product = (unsigned_p
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? V8_4 (x, 1) * V8_4 (y, 1)
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: EXTEND32 (x) * EXTEND32 (y));
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result = (subtract_p ? lhs - product : lhs + product);
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if (saturate_p)
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{
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/* Saturate the result to 32 bits. An unsigned, unsaturated
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result is zero-extended to 64 bits, but unsigned overflow
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causes all 64 bits to be set. */
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if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
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result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
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else if (unsigned_p && (result >> 32) != 0)
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result = (unsigned64) 0 - 1;
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}
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TRACE_ALU_RESULT (result);
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if (double_p)
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LO = result;
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else
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{
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LO = EXTEND32 (result);
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HI = EXTEND32 (VH4_8 (result));
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}
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if (rd != 0)
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GPR[rd] = store_hi_p ? HI : LO;
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}
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// VR4100 instructions.
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000000,5.RS,5.RT,00000,00000,101000::32::MADD16
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"madd16 r<RS>, r<RT>"
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*vr4100:
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{
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do_vr_mul_op (SD_, 0, RS, RT,
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1 /* accumulate */,
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0 /* store in LO */,
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0 /* signed arithmetic */,
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0 /* don't saturate */,
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0 /* don't subtract */,
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1 /* short */,
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0 /* single */);
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}
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000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
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"dmadd16 r<RS>, r<RT>"
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*vr4100:
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{
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do_vr_mul_op (SD_, 0, RS, RT,
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1 /* accumulate */,
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0 /* store in LO */,
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0 /* signed arithmetic */,
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0 /* don't saturate */,
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0 /* don't subtract */,
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1 /* short */,
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1 /* double */);
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}
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// VR4120 and VR4130 instructions.
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000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
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"dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
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*vr4120:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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1 /* accumulate */,
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MFHI, UNS, SAT,
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0 /* don't subtract */,
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SAT /* short */,
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1 /* double */);
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}
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000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
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"macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
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*vr4120:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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1 /* accumulate */,
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MFHI, UNS, SAT,
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0 /* don't subtract */,
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SAT /* short */,
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0 /* single */);
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}
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// VR5400 and VR5500 instructions.
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000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
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"mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
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*vr5400:
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*vr5500:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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0 /* don't accumulate */,
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MFHI, UNS,
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0 /* don't saturate */,
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0 /* don't subtract */,
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0 /* not short */,
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0 /* single */);
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}
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000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
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"muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
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*vr5400:
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*vr5500:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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0 /* don't accumulate */,
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MFHI, UNS,
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0 /* don't saturate */,
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1 /* subtract */,
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0 /* not short */,
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0 /* single */);
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}
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000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
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"macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
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*vr5400:
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*vr5500:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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1 /* accumulate */,
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MFHI, UNS,
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0 /* don't saturate */,
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0 /* don't subtract */,
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0 /* not short */,
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0 /* single */);
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}
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000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
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"msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
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*vr5400:
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*vr5500:
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{
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do_vr_mul_op (SD_, RD, RS, RT,
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1 /* accumulate */,
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MFHI, UNS,
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0 /* don't saturate */,
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1 /* subtract */,
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0 /* not short */,
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0 /* single */);
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}
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010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
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"luxc1 f<FD>, r<INDEX>(r<BASE>)"
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*vr5500:
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{
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check_fpu (SD_);
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COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
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(GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
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}
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010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
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"suxc1 f<FS>, r<INDEX>(r<BASE>)"
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*vr5500:
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{
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check_fpu (SD_);
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do_store (SD_, AccessLength_DOUBLEWORD,
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(GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
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COP_SD (1, FS));
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}
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010000,1,19.*,100000:COP0:32::WAIT
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"wait"
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*vr5500:
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011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
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"mfdr r<RT>, r<DR>"
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*vr5400:
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*vr5500:
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011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
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"mtdr r<RT>, r<DR>"
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*vr5400:
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*vr5500:
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011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
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"dret"
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*vr5400:
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*vr5500:
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