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631 lines
18 KiB
C
631 lines
18 KiB
C
/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-dis.in isn't
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "fr30-desc.h"
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#include "fr30-opc.h"
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#include "opintl.h"
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG _("*unknown*")
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static void print_normal
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PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
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static void print_address
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PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
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static void print_keyword
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PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
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static void print_insn_normal
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PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
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bfd_vma, int));
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static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
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disassemble_info *, char *, int));
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static int default_print_insn
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PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
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/* -- disassembler routines inserted here */
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/* -- dis.c */
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static void
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print_register_list (dis_info, value, offset, load_store)
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PTR dis_info;
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long value;
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long offset;
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int load_store; /* 0 == load, 1 == store */
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{
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disassemble_info *info = dis_info;
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int mask;
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int index = 0;
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char* comma = "";
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if (load_store)
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mask = 0x80;
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else
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mask = 1;
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if (value & mask)
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{
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(*info->fprintf_func) (info->stream, "r%i", index + offset);
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comma = ",";
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}
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for (index = 1; index <= 7; ++index)
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{
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if (load_store)
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mask >>= 1;
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else
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mask <<= 1;
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if (value & mask)
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{
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(*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
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comma = ",";
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}
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}
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}
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static void
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print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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print_register_list (dis_info, value, 8, 0/*load*/);
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}
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static void
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print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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print_register_list (dis_info, value, 0, 0/*load*/);
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}
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static void
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print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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print_register_list (dis_info, value, 8, 1/*store*/);
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}
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static void
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print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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print_register_list (dis_info, value, 0, 1/*store*/);
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}
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static void
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print_m4 (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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/* -- */
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/* Main entry point for printing operands.
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XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
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of dis-asm.h on cgen.h.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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void
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fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
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CGEN_CPU_DESC cd;
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int opindex;
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PTR xinfo;
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CGEN_FIELDS *fields;
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void const *attrs;
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bfd_vma pc;
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int length;
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{
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disassemble_info *info = (disassemble_info *) xinfo;
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switch (opindex)
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{
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case FR30_OPERAND_CRI :
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print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
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break;
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case FR30_OPERAND_CRJ :
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print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
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break;
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case FR30_OPERAND_R13 :
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print_keyword (cd, info, & fr30_cgen_opval_h_r13, fields->f_nil, 0);
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break;
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case FR30_OPERAND_R14 :
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print_keyword (cd, info, & fr30_cgen_opval_h_r14, fields->f_nil, 0);
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break;
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case FR30_OPERAND_R15 :
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print_keyword (cd, info, & fr30_cgen_opval_h_r15, fields->f_nil, 0);
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break;
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case FR30_OPERAND_RI :
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print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
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break;
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case FR30_OPERAND_RIC :
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print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
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break;
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case FR30_OPERAND_RJ :
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print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
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break;
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case FR30_OPERAND_RJC :
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print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
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break;
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case FR30_OPERAND_RS1 :
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print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
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break;
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case FR30_OPERAND_RS2 :
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print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
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break;
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case FR30_OPERAND_CC :
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print_normal (cd, info, fields->f_cc, 0, pc, length);
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break;
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case FR30_OPERAND_CCC :
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print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_DIR10 :
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print_normal (cd, info, fields->f_dir10, 0, pc, length);
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break;
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case FR30_OPERAND_DIR8 :
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print_normal (cd, info, fields->f_dir8, 0, pc, length);
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break;
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case FR30_OPERAND_DIR9 :
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print_normal (cd, info, fields->f_dir9, 0, pc, length);
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break;
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case FR30_OPERAND_DISP10 :
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print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_DISP8 :
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print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_DISP9 :
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print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_I20 :
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print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
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break;
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case FR30_OPERAND_I32 :
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print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
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break;
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case FR30_OPERAND_I8 :
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print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_LABEL12 :
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print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case FR30_OPERAND_LABEL9 :
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print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case FR30_OPERAND_M4 :
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print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_PS :
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print_keyword (cd, info, & fr30_cgen_opval_h_ps, fields->f_nil, 0);
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break;
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case FR30_OPERAND_REGLIST_HI_LD :
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print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
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break;
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case FR30_OPERAND_REGLIST_HI_ST :
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print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
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break;
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case FR30_OPERAND_REGLIST_LOW_LD :
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print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
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break;
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case FR30_OPERAND_REGLIST_LOW_ST :
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print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
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break;
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case FR30_OPERAND_S10 :
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print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_U10 :
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print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_U4 :
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print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_U4C :
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print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_U8 :
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print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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case FR30_OPERAND_UDISP6 :
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print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
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break;
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default :
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/* xgettext:c-format */
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fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
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opindex);
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abort ();
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}
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}
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cgen_print_fn * const fr30_cgen_print_handlers[] =
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{
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print_insn_normal,
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};
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void
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fr30_cgen_init_dis (cd)
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CGEN_CPU_DESC cd;
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{
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fr30_cgen_init_opcode_table (cd);
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fr30_cgen_init_ibld_table (cd);
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cd->print_handlers = & fr30_cgen_print_handlers[0];
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cd->print_operand = fr30_cgen_print_operand;
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}
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/* Default print handler. */
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static void
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print_normal (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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#ifdef CGEN_PRINT_NORMAL
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CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
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#endif
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/* Print the operand as directed by the attributes. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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; /* nothing to do */
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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(*info->fprintf_func) (info->stream, "%ld", value);
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else
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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}
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/* Default address handler. */
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static void
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print_address (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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bfd_vma value;
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unsigned int attrs;
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bfd_vma pc;
|
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int length;
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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|
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#ifdef CGEN_PRINT_ADDRESS
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CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
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#endif
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|
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/* Print the operand as directed by the attributes. */
|
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
|
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; /* nothing to do */
|
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
|
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(*info->print_address_func) (value, info);
|
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
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(*info->print_address_func) (value, info);
|
||
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
|
||
(*info->fprintf_func) (info->stream, "%ld", (long) value);
|
||
else
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||
(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
|
||
}
|
||
|
||
/* Keyword print handler. */
|
||
|
||
static void
|
||
print_keyword (cd, dis_info, keyword_table, value, attrs)
|
||
CGEN_CPU_DESC cd;
|
||
PTR dis_info;
|
||
CGEN_KEYWORD *keyword_table;
|
||
long value;
|
||
unsigned int attrs;
|
||
{
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
const CGEN_KEYWORD_ENTRY *ke;
|
||
|
||
ke = cgen_keyword_lookup_value (keyword_table, value);
|
||
if (ke != NULL)
|
||
(*info->fprintf_func) (info->stream, "%s", ke->name);
|
||
else
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||
(*info->fprintf_func) (info->stream, "???");
|
||
}
|
||
|
||
/* Default insn printer.
|
||
|
||
DIS_INFO is defined as `PTR' so the disassembler needn't know anything
|
||
about disassemble_info. */
|
||
|
||
static void
|
||
print_insn_normal (cd, dis_info, insn, fields, pc, length)
|
||
CGEN_CPU_DESC cd;
|
||
PTR dis_info;
|
||
const CGEN_INSN *insn;
|
||
CGEN_FIELDS *fields;
|
||
bfd_vma pc;
|
||
int length;
|
||
{
|
||
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||
disassemble_info *info = (disassemble_info *) dis_info;
|
||
const unsigned char *syn;
|
||
|
||
CGEN_INIT_PRINT (cd);
|
||
|
||
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||
{
|
||
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
|
||
continue;
|
||
}
|
||
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||
{
|
||
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
|
||
continue;
|
||
}
|
||
|
||
/* We have an operand. */
|
||
fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
|
||
fields, CGEN_INSN_ATTRS (insn), pc, length);
|
||
}
|
||
}
|
||
|
||
/* Utility to print an insn.
|
||
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
|
||
The result is the size of the insn in bytes or zero for an unknown insn
|
||
or -1 if an error occurs fetching data (memory_error_func will have
|
||
been called). */
|
||
|
||
static int
|
||
print_insn (cd, pc, info, buf, buflen)
|
||
CGEN_CPU_DESC cd;
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
char *buf;
|
||
int buflen;
|
||
{
|
||
unsigned long insn_value;
|
||
const CGEN_INSN_LIST *insn_list;
|
||
CGEN_EXTRACT_INFO ex_info;
|
||
|
||
ex_info.dis_info = info;
|
||
ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
|
||
ex_info.insn_bytes = buf;
|
||
|
||
switch (buflen)
|
||
{
|
||
case 1:
|
||
insn_value = buf[0];
|
||
break;
|
||
case 2:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||
break;
|
||
case 4:
|
||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
|
||
/* The instructions are stored in hash lists.
|
||
Pick the first one and keep trying until we find the right one. */
|
||
|
||
insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
|
||
while (insn_list != NULL)
|
||
{
|
||
const CGEN_INSN *insn = insn_list->insn;
|
||
CGEN_FIELDS fields;
|
||
int length;
|
||
|
||
#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
|
||
/* Supported by this cpu? */
|
||
if (! fr30_cgen_insn_supported (cd, insn))
|
||
continue;
|
||
#endif
|
||
|
||
/* Basic bit mask must be correct. */
|
||
/* ??? May wish to allow target to defer this check until the extract
|
||
handler. */
|
||
if ((insn_value & CGEN_INSN_BASE_MASK (insn))
|
||
== CGEN_INSN_BASE_VALUE (insn))
|
||
{
|
||
/* Printing is handled in two passes. The first pass parses the
|
||
machine insn and extracts the fields. The second pass prints
|
||
them. */
|
||
|
||
length = CGEN_EXTRACT_FN (cd, insn)
|
||
(cd, insn, &ex_info, insn_value, &fields, pc);
|
||
/* length < 0 -> error */
|
||
if (length < 0)
|
||
return length;
|
||
if (length > 0)
|
||
{
|
||
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
|
||
/* length is in bits, result is in bytes */
|
||
return length / 8;
|
||
}
|
||
}
|
||
|
||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Default value for CGEN_PRINT_INSN.
|
||
The result is the size of the insn in bytes or zero for an unknown insn
|
||
or -1 if an error occured fetching bytes. */
|
||
|
||
#ifndef CGEN_PRINT_INSN
|
||
#define CGEN_PRINT_INSN default_print_insn
|
||
#endif
|
||
|
||
static int
|
||
default_print_insn (cd, pc, info)
|
||
CGEN_CPU_DESC cd;
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
{
|
||
char buf[CGEN_MAX_INSN_SIZE];
|
||
int status;
|
||
|
||
/* Read the base part of the insn. */
|
||
|
||
status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
|
||
if (status != 0)
|
||
{
|
||
(*info->memory_error_func) (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
|
||
}
|
||
|
||
/* Main entry point.
|
||
Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction (in bytes). */
|
||
|
||
int
|
||
print_insn_fr30 (pc, info)
|
||
bfd_vma pc;
|
||
disassemble_info *info;
|
||
{
|
||
static CGEN_CPU_DESC cd = 0;
|
||
static prev_isa,prev_mach,prev_endian;
|
||
int length;
|
||
int isa,mach;
|
||
int endian = (info->endian == BFD_ENDIAN_BIG
|
||
? CGEN_ENDIAN_BIG
|
||
: CGEN_ENDIAN_LITTLE);
|
||
enum bfd_architecture arch;
|
||
|
||
/* ??? gdb will set mach but leave the architecture as "unknown" */
|
||
#ifndef CGEN_BFD_ARCH
|
||
#define CGEN_BFD_ARCH bfd_arch_fr30
|
||
#endif
|
||
arch = info->arch;
|
||
if (arch == bfd_arch_unknown)
|
||
arch = CGEN_BFD_ARCH;
|
||
|
||
/* There's no standard way to compute the isa number (e.g. for arm thumb)
|
||
so we leave it to the target. */
|
||
#ifdef CGEN_COMPUTE_ISA
|
||
isa = CGEN_COMPUTE_ISA (info);
|
||
#else
|
||
isa = 0;
|
||
#endif
|
||
|
||
mach = info->mach;
|
||
|
||
/* If we've switched cpu's, close the current table and open a new one. */
|
||
if (cd
|
||
&& (isa != prev_isa
|
||
|| mach != prev_mach
|
||
|| endian != prev_endian))
|
||
{
|
||
fr30_cgen_cpu_close (cd);
|
||
cd = 0;
|
||
}
|
||
|
||
/* If we haven't initialized yet, initialize the opcode table. */
|
||
if (! cd)
|
||
{
|
||
const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
|
||
const char *mach_name;
|
||
|
||
if (!arch_type)
|
||
abort ();
|
||
mach_name = arch_type->printable_name;
|
||
|
||
prev_isa = isa;
|
||
prev_mach = mach;
|
||
prev_endian = endian;
|
||
cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
|
||
CGEN_CPU_OPEN_BFDMACH, mach_name,
|
||
CGEN_CPU_OPEN_ENDIAN, prev_endian,
|
||
CGEN_CPU_OPEN_END);
|
||
if (!cd)
|
||
abort ();
|
||
fr30_cgen_init_dis (cd);
|
||
}
|
||
|
||
/* We try to have as much common code as possible.
|
||
But at this point some targets need to take over. */
|
||
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||
but if not possible try to move this hook elsewhere rather than
|
||
have two hooks. */
|
||
length = CGEN_PRINT_INSN (cd, pc, info);
|
||
if (length > 0)
|
||
return length;
|
||
if (length < 0)
|
||
return -1;
|
||
|
||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||
return cd->default_insn_bitsize / 8;
|
||
}
|