mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-21 01:12:32 +08:00
43234a1e14
binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
855 lines
22 KiB
C
855 lines
22 KiB
C
/* Declarations for Intel 80386 opcode table
|
|
Copyright 2007, 2008, 2009, 2010, 2012
|
|
Free Software Foundation, Inc.
|
|
|
|
This file is part of the GNU opcodes library.
|
|
|
|
This library is free software; you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation; either version 3, or (at your option)
|
|
any later version.
|
|
|
|
It is distributed in the hope that it will be useful, but WITHOUT
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
License for more details.
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
along with GAS; see the file COPYING. If not, write to the Free
|
|
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
|
02110-1301, USA. */
|
|
|
|
#include "opcode/i386.h"
|
|
#ifdef HAVE_LIMITS_H
|
|
#include <limits.h>
|
|
#endif
|
|
|
|
#ifndef CHAR_BIT
|
|
#define CHAR_BIT 8
|
|
#endif
|
|
|
|
/* Position of cpu flags bitfiled. */
|
|
|
|
enum
|
|
{
|
|
/* i186 or better required */
|
|
Cpu186 = 0,
|
|
/* i286 or better required */
|
|
Cpu286,
|
|
/* i386 or better required */
|
|
Cpu386,
|
|
/* i486 or better required */
|
|
Cpu486,
|
|
/* i585 or better required */
|
|
Cpu586,
|
|
/* i686 or better required */
|
|
Cpu686,
|
|
/* CLFLUSH Instruction support required */
|
|
CpuClflush,
|
|
/* NOP Instruction support required */
|
|
CpuNop,
|
|
/* SYSCALL Instructions support required */
|
|
CpuSYSCALL,
|
|
/* Floating point support required */
|
|
Cpu8087,
|
|
/* i287 support required */
|
|
Cpu287,
|
|
/* i387 support required */
|
|
Cpu387,
|
|
/* i686 and floating point support required */
|
|
Cpu687,
|
|
/* SSE3 and floating point support required */
|
|
CpuFISTTP,
|
|
/* MMX support required */
|
|
CpuMMX,
|
|
/* SSE support required */
|
|
CpuSSE,
|
|
/* SSE2 support required */
|
|
CpuSSE2,
|
|
/* 3dnow! support required */
|
|
Cpu3dnow,
|
|
/* 3dnow! Extensions support required */
|
|
Cpu3dnowA,
|
|
/* SSE3 support required */
|
|
CpuSSE3,
|
|
/* VIA PadLock required */
|
|
CpuPadLock,
|
|
/* AMD Secure Virtual Machine Ext-s required */
|
|
CpuSVME,
|
|
/* VMX Instructions required */
|
|
CpuVMX,
|
|
/* SMX Instructions required */
|
|
CpuSMX,
|
|
/* SSSE3 support required */
|
|
CpuSSSE3,
|
|
/* SSE4a support required */
|
|
CpuSSE4a,
|
|
/* ABM New Instructions required */
|
|
CpuABM,
|
|
/* SSE4.1 support required */
|
|
CpuSSE4_1,
|
|
/* SSE4.2 support required */
|
|
CpuSSE4_2,
|
|
/* AVX support required */
|
|
CpuAVX,
|
|
/* AVX2 support required */
|
|
CpuAVX2,
|
|
/* Intel AVX-512 Foundation Instructions support required */
|
|
CpuAVX512F,
|
|
/* Intel AVX-512 Conflict Detection Instructions support required */
|
|
CpuAVX512CD,
|
|
/* Intel AVX-512 Exponential and Reciprocal Instructions support
|
|
required */
|
|
CpuAVX512ER,
|
|
/* Intel AVX-512 Prefetch Instructions support required */
|
|
CpuAVX512PF,
|
|
/* Intel L1OM support required */
|
|
CpuL1OM,
|
|
/* Intel K1OM support required */
|
|
CpuK1OM,
|
|
/* Xsave/xrstor New Instructions support required */
|
|
CpuXsave,
|
|
/* Xsaveopt New Instructions support required */
|
|
CpuXsaveopt,
|
|
/* AES support required */
|
|
CpuAES,
|
|
/* PCLMUL support required */
|
|
CpuPCLMUL,
|
|
/* FMA support required */
|
|
CpuFMA,
|
|
/* FMA4 support required */
|
|
CpuFMA4,
|
|
/* XOP support required */
|
|
CpuXOP,
|
|
/* LWP support required */
|
|
CpuLWP,
|
|
/* BMI support required */
|
|
CpuBMI,
|
|
/* TBM support required */
|
|
CpuTBM,
|
|
/* MOVBE Instruction support required */
|
|
CpuMovbe,
|
|
/* CMPXCHG16B instruction support required. */
|
|
CpuCX16,
|
|
/* EPT Instructions required */
|
|
CpuEPT,
|
|
/* RDTSCP Instruction support required */
|
|
CpuRdtscp,
|
|
/* FSGSBASE Instructions required */
|
|
CpuFSGSBase,
|
|
/* RDRND Instructions required */
|
|
CpuRdRnd,
|
|
/* F16C Instructions required */
|
|
CpuF16C,
|
|
/* Intel BMI2 support required */
|
|
CpuBMI2,
|
|
/* LZCNT support required */
|
|
CpuLZCNT,
|
|
/* HLE support required */
|
|
CpuHLE,
|
|
/* RTM support required */
|
|
CpuRTM,
|
|
/* INVPCID Instructions required */
|
|
CpuINVPCID,
|
|
/* VMFUNC Instruction required */
|
|
CpuVMFUNC,
|
|
/* Intel MPX Instructions required */
|
|
CpuMPX,
|
|
/* 64bit support available, used by -march= in assembler. */
|
|
CpuLM,
|
|
/* RDRSEED instruction required. */
|
|
CpuRDSEED,
|
|
/* Multi-presisionn add-carry instructions are required. */
|
|
CpuADX,
|
|
/* Supports prefetchw and prefetch instructions. */
|
|
CpuPRFCHW,
|
|
/* SMAP instructions required. */
|
|
CpuSMAP,
|
|
/* SHA instructions required. */
|
|
CpuSHA,
|
|
/* VREX support required */
|
|
CpuVREX,
|
|
/* 64bit support required */
|
|
Cpu64,
|
|
/* Not supported in the 64bit mode */
|
|
CpuNo64,
|
|
/* The last bitfield in i386_cpu_flags. */
|
|
CpuMax = CpuNo64
|
|
};
|
|
|
|
#define CpuNumOfUints \
|
|
(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
|
#define CpuNumOfBits \
|
|
(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
|
|
|
/* If you get a compiler error for zero width of the unused field,
|
|
comment it out. */
|
|
#define CpuUnused (CpuMax + 1)
|
|
|
|
/* We can check if an instruction is available with array instead
|
|
of bitfield. */
|
|
typedef union i386_cpu_flags
|
|
{
|
|
struct
|
|
{
|
|
unsigned int cpui186:1;
|
|
unsigned int cpui286:1;
|
|
unsigned int cpui386:1;
|
|
unsigned int cpui486:1;
|
|
unsigned int cpui586:1;
|
|
unsigned int cpui686:1;
|
|
unsigned int cpuclflush:1;
|
|
unsigned int cpunop:1;
|
|
unsigned int cpusyscall:1;
|
|
unsigned int cpu8087:1;
|
|
unsigned int cpu287:1;
|
|
unsigned int cpu387:1;
|
|
unsigned int cpu687:1;
|
|
unsigned int cpufisttp:1;
|
|
unsigned int cpummx:1;
|
|
unsigned int cpusse:1;
|
|
unsigned int cpusse2:1;
|
|
unsigned int cpua3dnow:1;
|
|
unsigned int cpua3dnowa:1;
|
|
unsigned int cpusse3:1;
|
|
unsigned int cpupadlock:1;
|
|
unsigned int cpusvme:1;
|
|
unsigned int cpuvmx:1;
|
|
unsigned int cpusmx:1;
|
|
unsigned int cpussse3:1;
|
|
unsigned int cpusse4a:1;
|
|
unsigned int cpuabm:1;
|
|
unsigned int cpusse4_1:1;
|
|
unsigned int cpusse4_2:1;
|
|
unsigned int cpuavx:1;
|
|
unsigned int cpuavx2:1;
|
|
unsigned int cpuavx512f:1;
|
|
unsigned int cpuavx512cd:1;
|
|
unsigned int cpuavx512er:1;
|
|
unsigned int cpuavx512pf:1;
|
|
unsigned int cpul1om:1;
|
|
unsigned int cpuk1om:1;
|
|
unsigned int cpuxsave:1;
|
|
unsigned int cpuxsaveopt:1;
|
|
unsigned int cpuaes:1;
|
|
unsigned int cpupclmul:1;
|
|
unsigned int cpufma:1;
|
|
unsigned int cpufma4:1;
|
|
unsigned int cpuxop:1;
|
|
unsigned int cpulwp:1;
|
|
unsigned int cpubmi:1;
|
|
unsigned int cputbm:1;
|
|
unsigned int cpumovbe:1;
|
|
unsigned int cpucx16:1;
|
|
unsigned int cpuept:1;
|
|
unsigned int cpurdtscp:1;
|
|
unsigned int cpufsgsbase:1;
|
|
unsigned int cpurdrnd:1;
|
|
unsigned int cpuf16c:1;
|
|
unsigned int cpubmi2:1;
|
|
unsigned int cpulzcnt:1;
|
|
unsigned int cpuhle:1;
|
|
unsigned int cpurtm:1;
|
|
unsigned int cpuinvpcid:1;
|
|
unsigned int cpuvmfunc:1;
|
|
unsigned int cpumpx:1;
|
|
unsigned int cpulm:1;
|
|
unsigned int cpurdseed:1;
|
|
unsigned int cpuadx:1;
|
|
unsigned int cpuprfchw:1;
|
|
unsigned int cpusmap:1;
|
|
unsigned int cpusha:1;
|
|
unsigned int cpuvrex:1;
|
|
unsigned int cpu64:1;
|
|
unsigned int cpuno64:1;
|
|
#ifdef CpuUnused
|
|
unsigned int unused:(CpuNumOfBits - CpuUnused);
|
|
#endif
|
|
} bitfield;
|
|
unsigned int array[CpuNumOfUints];
|
|
} i386_cpu_flags;
|
|
|
|
/* Position of opcode_modifier bits. */
|
|
|
|
enum
|
|
{
|
|
/* has direction bit. */
|
|
D = 0,
|
|
/* set if operands can be words or dwords encoded the canonical way */
|
|
W,
|
|
/* Skip the current insn and use the next insn in i386-opc.tbl to swap
|
|
operand in encoding. */
|
|
S,
|
|
/* insn has a modrm byte. */
|
|
Modrm,
|
|
/* register is in low 3 bits of opcode */
|
|
ShortForm,
|
|
/* special case for jump insns. */
|
|
Jump,
|
|
/* call and jump */
|
|
JumpDword,
|
|
/* loop and jecxz */
|
|
JumpByte,
|
|
/* special case for intersegment leaps/calls */
|
|
JumpInterSegment,
|
|
/* FP insn memory format bit, sized by 0x4 */
|
|
FloatMF,
|
|
/* src/dest swap for floats. */
|
|
FloatR,
|
|
/* has float insn direction bit. */
|
|
FloatD,
|
|
/* needs size prefix if in 32-bit mode */
|
|
Size16,
|
|
/* needs size prefix if in 16-bit mode */
|
|
Size32,
|
|
/* needs size prefix if in 64-bit mode */
|
|
Size64,
|
|
/* check register size. */
|
|
CheckRegSize,
|
|
/* instruction ignores operand size prefix and in Intel mode ignores
|
|
mnemonic size suffix check. */
|
|
IgnoreSize,
|
|
/* default insn size depends on mode */
|
|
DefaultSize,
|
|
/* b suffix on instruction illegal */
|
|
No_bSuf,
|
|
/* w suffix on instruction illegal */
|
|
No_wSuf,
|
|
/* l suffix on instruction illegal */
|
|
No_lSuf,
|
|
/* s suffix on instruction illegal */
|
|
No_sSuf,
|
|
/* q suffix on instruction illegal */
|
|
No_qSuf,
|
|
/* long double suffix on instruction illegal */
|
|
No_ldSuf,
|
|
/* instruction needs FWAIT */
|
|
FWait,
|
|
/* quick test for string instructions */
|
|
IsString,
|
|
/* quick test if branch instruction is MPX supported */
|
|
BNDPrefixOk,
|
|
/* quick test for lockable instructions */
|
|
IsLockable,
|
|
/* fake an extra reg operand for clr, imul and special register
|
|
processing for some instructions. */
|
|
RegKludge,
|
|
/* The first operand must be xmm0 */
|
|
FirstXmm0,
|
|
/* An implicit xmm0 as the first operand */
|
|
Implicit1stXmm0,
|
|
/* The HLE prefix is OK:
|
|
1. With a LOCK prefix.
|
|
2. With or without a LOCK prefix.
|
|
3. With a RELEASE (0xf3) prefix.
|
|
*/
|
|
#define HLEPrefixNone 0
|
|
#define HLEPrefixLock 1
|
|
#define HLEPrefixAny 2
|
|
#define HLEPrefixRelease 3
|
|
HLEPrefixOk,
|
|
/* An instruction on which a "rep" prefix is acceptable. */
|
|
RepPrefixOk,
|
|
/* Convert to DWORD */
|
|
ToDword,
|
|
/* Convert to QWORD */
|
|
ToQword,
|
|
/* Address prefix changes operand 0 */
|
|
AddrPrefixOp0,
|
|
/* opcode is a prefix */
|
|
IsPrefix,
|
|
/* instruction has extension in 8 bit imm */
|
|
ImmExt,
|
|
/* instruction don't need Rex64 prefix. */
|
|
NoRex64,
|
|
/* instruction require Rex64 prefix. */
|
|
Rex64,
|
|
/* deprecated fp insn, gets a warning */
|
|
Ugh,
|
|
/* insn has VEX prefix:
|
|
1: 128bit VEX prefix.
|
|
2: 256bit VEX prefix.
|
|
3: Scalar VEX prefix.
|
|
*/
|
|
#define VEX128 1
|
|
#define VEX256 2
|
|
#define VEXScalar 3
|
|
Vex,
|
|
/* How to encode VEX.vvvv:
|
|
0: VEX.vvvv must be 1111b.
|
|
1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
|
|
the content of source registers will be preserved.
|
|
VEX.DDS. The second register operand is encoded in VEX.vvvv
|
|
where the content of first source register will be overwritten
|
|
by the result.
|
|
VEX.NDD2. The second destination register operand is encoded in
|
|
VEX.vvvv for instructions with 2 destination register operands.
|
|
For assembler, there are no difference between VEX.NDS, VEX.DDS
|
|
and VEX.NDD2.
|
|
2. VEX.NDD. Register destination is encoded in VEX.vvvv for
|
|
instructions with 1 destination register operand.
|
|
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
|
|
of the operands can access a memory location.
|
|
*/
|
|
#define VEXXDS 1
|
|
#define VEXNDD 2
|
|
#define VEXLWP 3
|
|
VexVVVV,
|
|
/* How the VEX.W bit is used:
|
|
0: Set by the REX.W bit.
|
|
1: VEX.W0. Should always be 0.
|
|
2: VEX.W1. Should always be 1.
|
|
*/
|
|
#define VEXW0 1
|
|
#define VEXW1 2
|
|
VexW,
|
|
/* VEX opcode prefix:
|
|
0: VEX 0x0F opcode prefix.
|
|
1: VEX 0x0F38 opcode prefix.
|
|
2: VEX 0x0F3A opcode prefix
|
|
3: XOP 0x08 opcode prefix.
|
|
4: XOP 0x09 opcode prefix
|
|
5: XOP 0x0A opcode prefix.
|
|
*/
|
|
#define VEX0F 0
|
|
#define VEX0F38 1
|
|
#define VEX0F3A 2
|
|
#define XOP08 3
|
|
#define XOP09 4
|
|
#define XOP0A 5
|
|
VexOpcode,
|
|
/* number of VEX source operands:
|
|
0: <= 2 source operands.
|
|
1: 2 XOP source operands.
|
|
2: 3 source operands.
|
|
*/
|
|
#define XOP2SOURCES 1
|
|
#define VEX3SOURCES 2
|
|
VexSources,
|
|
/* instruction has VEX 8 bit imm */
|
|
VexImmExt,
|
|
/* Instruction with vector SIB byte:
|
|
1: 128bit vector register.
|
|
2: 256bit vector register.
|
|
3: 512bit vector register.
|
|
*/
|
|
#define VecSIB128 1
|
|
#define VecSIB256 2
|
|
#define VecSIB512 3
|
|
VecSIB,
|
|
/* SSE to AVX support required */
|
|
SSE2AVX,
|
|
/* No AVX equivalent */
|
|
NoAVX,
|
|
|
|
/* insn has EVEX prefix:
|
|
1: 512bit EVEX prefix.
|
|
2: 128bit EVEX prefix.
|
|
3: 256bit EVEX prefix.
|
|
4: Length-ignored (LIG) EVEX prefix.
|
|
*/
|
|
#define EVEX512 1
|
|
#define EVEX128 2
|
|
#define EVEX256 3
|
|
#define EVEXLIG 4
|
|
EVex,
|
|
|
|
/* AVX512 masking support:
|
|
1: Zeroing-masking.
|
|
2: Merging-masking.
|
|
3: Both zeroing and merging masking.
|
|
*/
|
|
#define ZEROING_MASKING 1
|
|
#define MERGING_MASKING 2
|
|
#define BOTH_MASKING 3
|
|
Masking,
|
|
|
|
/* Input element size of vector insn:
|
|
0: 32bit.
|
|
1: 64bit.
|
|
*/
|
|
VecESize,
|
|
|
|
/* Broadcast factor.
|
|
0: No broadcast.
|
|
1: 1to16 broadcast.
|
|
2: 1to8 broadcast.
|
|
*/
|
|
#define NO_BROADCAST 0
|
|
#define BROADCAST_1TO16 1
|
|
#define BROADCAST_1TO8 2
|
|
Broadcast,
|
|
|
|
/* Static rounding control is supported. */
|
|
StaticRounding,
|
|
|
|
/* Supress All Exceptions is supported. */
|
|
SAE,
|
|
|
|
/* Copressed Disp8*N attribute. */
|
|
Disp8MemShift,
|
|
|
|
/* Default mask isn't allowed. */
|
|
NoDefMask,
|
|
|
|
/* Compatible with old (<= 2.8.1) versions of gcc */
|
|
OldGcc,
|
|
/* AT&T mnemonic. */
|
|
ATTMnemonic,
|
|
/* AT&T syntax. */
|
|
ATTSyntax,
|
|
/* Intel syntax. */
|
|
IntelSyntax,
|
|
/* The last bitfield in i386_opcode_modifier. */
|
|
Opcode_Modifier_Max
|
|
};
|
|
|
|
typedef struct i386_opcode_modifier
|
|
{
|
|
unsigned int d:1;
|
|
unsigned int w:1;
|
|
unsigned int s:1;
|
|
unsigned int modrm:1;
|
|
unsigned int shortform:1;
|
|
unsigned int jump:1;
|
|
unsigned int jumpdword:1;
|
|
unsigned int jumpbyte:1;
|
|
unsigned int jumpintersegment:1;
|
|
unsigned int floatmf:1;
|
|
unsigned int floatr:1;
|
|
unsigned int floatd:1;
|
|
unsigned int size16:1;
|
|
unsigned int size32:1;
|
|
unsigned int size64:1;
|
|
unsigned int checkregsize:1;
|
|
unsigned int ignoresize:1;
|
|
unsigned int defaultsize:1;
|
|
unsigned int no_bsuf:1;
|
|
unsigned int no_wsuf:1;
|
|
unsigned int no_lsuf:1;
|
|
unsigned int no_ssuf:1;
|
|
unsigned int no_qsuf:1;
|
|
unsigned int no_ldsuf:1;
|
|
unsigned int fwait:1;
|
|
unsigned int isstring:1;
|
|
unsigned int bndprefixok:1;
|
|
unsigned int islockable:1;
|
|
unsigned int regkludge:1;
|
|
unsigned int firstxmm0:1;
|
|
unsigned int implicit1stxmm0:1;
|
|
unsigned int hleprefixok:2;
|
|
unsigned int repprefixok:1;
|
|
unsigned int todword:1;
|
|
unsigned int toqword:1;
|
|
unsigned int addrprefixop0:1;
|
|
unsigned int isprefix:1;
|
|
unsigned int immext:1;
|
|
unsigned int norex64:1;
|
|
unsigned int rex64:1;
|
|
unsigned int ugh:1;
|
|
unsigned int vex:2;
|
|
unsigned int vexvvvv:2;
|
|
unsigned int vexw:2;
|
|
unsigned int vexopcode:3;
|
|
unsigned int vexsources:2;
|
|
unsigned int veximmext:1;
|
|
unsigned int vecsib:2;
|
|
unsigned int sse2avx:1;
|
|
unsigned int noavx:1;
|
|
unsigned int evex:3;
|
|
unsigned int masking:2;
|
|
unsigned int vecesize:1;
|
|
unsigned int broadcast:3;
|
|
unsigned int staticrounding:1;
|
|
unsigned int sae:1;
|
|
unsigned int disp8memshift:3;
|
|
unsigned int nodefmask:1;
|
|
unsigned int oldgcc:1;
|
|
unsigned int attmnemonic:1;
|
|
unsigned int attsyntax:1;
|
|
unsigned int intelsyntax:1;
|
|
} i386_opcode_modifier;
|
|
|
|
/* Position of operand_type bits. */
|
|
|
|
enum
|
|
{
|
|
/* 8bit register */
|
|
Reg8 = 0,
|
|
/* 16bit register */
|
|
Reg16,
|
|
/* 32bit register */
|
|
Reg32,
|
|
/* 64bit register */
|
|
Reg64,
|
|
/* Floating pointer stack register */
|
|
FloatReg,
|
|
/* MMX register */
|
|
RegMMX,
|
|
/* SSE register */
|
|
RegXMM,
|
|
/* AVX registers */
|
|
RegYMM,
|
|
/* AVX512 registers */
|
|
RegZMM,
|
|
/* Vector Mask registers */
|
|
RegMask,
|
|
/* Control register */
|
|
Control,
|
|
/* Debug register */
|
|
Debug,
|
|
/* Test register */
|
|
Test,
|
|
/* 2 bit segment register */
|
|
SReg2,
|
|
/* 3 bit segment register */
|
|
SReg3,
|
|
/* 1 bit immediate */
|
|
Imm1,
|
|
/* 8 bit immediate */
|
|
Imm8,
|
|
/* 8 bit immediate sign extended */
|
|
Imm8S,
|
|
/* 16 bit immediate */
|
|
Imm16,
|
|
/* 32 bit immediate */
|
|
Imm32,
|
|
/* 32 bit immediate sign extended */
|
|
Imm32S,
|
|
/* 64 bit immediate */
|
|
Imm64,
|
|
/* 8bit/16bit/32bit displacements are used in different ways,
|
|
depending on the instruction. For jumps, they specify the
|
|
size of the PC relative displacement, for instructions with
|
|
memory operand, they specify the size of the offset relative
|
|
to the base register, and for instructions with memory offset
|
|
such as `mov 1234,%al' they specify the size of the offset
|
|
relative to the segment base. */
|
|
/* 8 bit displacement */
|
|
Disp8,
|
|
/* 16 bit displacement */
|
|
Disp16,
|
|
/* 32 bit displacement */
|
|
Disp32,
|
|
/* 32 bit signed displacement */
|
|
Disp32S,
|
|
/* 64 bit displacement */
|
|
Disp64,
|
|
/* Accumulator %al/%ax/%eax/%rax */
|
|
Acc,
|
|
/* Floating pointer top stack register %st(0) */
|
|
FloatAcc,
|
|
/* Register which can be used for base or index in memory operand. */
|
|
BaseIndex,
|
|
/* Register to hold in/out port addr = dx */
|
|
InOutPortReg,
|
|
/* Register to hold shift count = cl */
|
|
ShiftCount,
|
|
/* Absolute address for jump. */
|
|
JumpAbsolute,
|
|
/* String insn operand with fixed es segment */
|
|
EsSeg,
|
|
/* RegMem is for instructions with a modrm byte where the register
|
|
destination operand should be encoded in the mod and regmem fields.
|
|
Normally, it will be encoded in the reg field. We add a RegMem
|
|
flag to the destination register operand to indicate that it should
|
|
be encoded in the regmem field. */
|
|
RegMem,
|
|
/* Memory. */
|
|
Mem,
|
|
/* BYTE memory. */
|
|
Byte,
|
|
/* WORD memory. 2 byte */
|
|
Word,
|
|
/* DWORD memory. 4 byte */
|
|
Dword,
|
|
/* FWORD memory. 6 byte */
|
|
Fword,
|
|
/* QWORD memory. 8 byte */
|
|
Qword,
|
|
/* TBYTE memory. 10 byte */
|
|
Tbyte,
|
|
/* XMMWORD memory. */
|
|
Xmmword,
|
|
/* YMMWORD memory. */
|
|
Ymmword,
|
|
/* ZMMWORD memory. */
|
|
Zmmword,
|
|
/* Unspecified memory size. */
|
|
Unspecified,
|
|
/* Any memory size. */
|
|
Anysize,
|
|
|
|
/* Vector 4 bit immediate. */
|
|
Vec_Imm4,
|
|
|
|
/* Bound register. */
|
|
RegBND,
|
|
|
|
/* Vector 8bit displacement */
|
|
Vec_Disp8,
|
|
|
|
/* The last bitfield in i386_operand_type. */
|
|
OTMax
|
|
};
|
|
|
|
#define OTNumOfUints \
|
|
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
|
#define OTNumOfBits \
|
|
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
|
|
|
/* If you get a compiler error for zero width of the unused field,
|
|
comment it out. */
|
|
#define OTUnused (OTMax + 1)
|
|
|
|
typedef union i386_operand_type
|
|
{
|
|
struct
|
|
{
|
|
unsigned int reg8:1;
|
|
unsigned int reg16:1;
|
|
unsigned int reg32:1;
|
|
unsigned int reg64:1;
|
|
unsigned int floatreg:1;
|
|
unsigned int regmmx:1;
|
|
unsigned int regxmm:1;
|
|
unsigned int regymm:1;
|
|
unsigned int regzmm:1;
|
|
unsigned int regmask:1;
|
|
unsigned int control:1;
|
|
unsigned int debug:1;
|
|
unsigned int test:1;
|
|
unsigned int sreg2:1;
|
|
unsigned int sreg3:1;
|
|
unsigned int imm1:1;
|
|
unsigned int imm8:1;
|
|
unsigned int imm8s:1;
|
|
unsigned int imm16:1;
|
|
unsigned int imm32:1;
|
|
unsigned int imm32s:1;
|
|
unsigned int imm64:1;
|
|
unsigned int disp8:1;
|
|
unsigned int disp16:1;
|
|
unsigned int disp32:1;
|
|
unsigned int disp32s:1;
|
|
unsigned int disp64:1;
|
|
unsigned int acc:1;
|
|
unsigned int floatacc:1;
|
|
unsigned int baseindex:1;
|
|
unsigned int inoutportreg:1;
|
|
unsigned int shiftcount:1;
|
|
unsigned int jumpabsolute:1;
|
|
unsigned int esseg:1;
|
|
unsigned int regmem:1;
|
|
unsigned int mem:1;
|
|
unsigned int byte:1;
|
|
unsigned int word:1;
|
|
unsigned int dword:1;
|
|
unsigned int fword:1;
|
|
unsigned int qword:1;
|
|
unsigned int tbyte:1;
|
|
unsigned int xmmword:1;
|
|
unsigned int ymmword:1;
|
|
unsigned int zmmword:1;
|
|
unsigned int unspecified:1;
|
|
unsigned int anysize:1;
|
|
unsigned int vec_imm4:1;
|
|
unsigned int regbnd:1;
|
|
unsigned int vec_disp8:1;
|
|
#ifdef OTUnused
|
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
|
#endif
|
|
} bitfield;
|
|
unsigned int array[OTNumOfUints];
|
|
} i386_operand_type;
|
|
|
|
typedef struct insn_template
|
|
{
|
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
|
char *name;
|
|
|
|
/* how many operands */
|
|
unsigned int operands;
|
|
|
|
/* base_opcode is the fundamental opcode byte without optional
|
|
prefix(es). */
|
|
unsigned int base_opcode;
|
|
#define Opcode_D 0x2 /* Direction bit:
|
|
set if Reg --> Regmem;
|
|
unset if Regmem --> Reg. */
|
|
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
|
|
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
|
|
|
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
|
This field is also used to store the 8-bit opcode suffix for the
|
|
AMD 3DNow! instructions.
|
|
If this template has no extension opcode (the usual case) use None
|
|
Instructions */
|
|
unsigned int extension_opcode;
|
|
#define None 0xffff /* If no extension_opcode is possible. */
|
|
|
|
/* Opcode length. */
|
|
unsigned char opcode_length;
|
|
|
|
/* cpu feature flags */
|
|
i386_cpu_flags cpu_flags;
|
|
|
|
/* the bits in opcode_modifier are used to generate the final opcode from
|
|
the base_opcode. These bits also are used to detect alternate forms of
|
|
the same instruction */
|
|
i386_opcode_modifier opcode_modifier;
|
|
|
|
/* operand_types[i] describes the type of operand i. This is made
|
|
by OR'ing together all of the possible type masks. (e.g.
|
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
|
either a register or an immediate operand. */
|
|
i386_operand_type operand_types[MAX_OPERANDS];
|
|
}
|
|
insn_template;
|
|
|
|
extern const insn_template i386_optab[];
|
|
|
|
/* these are for register name --> number & type hash lookup */
|
|
typedef struct
|
|
{
|
|
char *reg_name;
|
|
i386_operand_type reg_type;
|
|
unsigned char reg_flags;
|
|
#define RegRex 0x1 /* Extended register. */
|
|
#define RegRex64 0x2 /* Extended 8 bit register. */
|
|
#define RegVRex 0x4 /* Extended vector register. */
|
|
unsigned char reg_num;
|
|
#define RegRip ((unsigned char ) ~0)
|
|
#define RegEip (RegRip - 1)
|
|
/* EIZ and RIZ are fake index registers. */
|
|
#define RegEiz (RegEip - 1)
|
|
#define RegRiz (RegEiz - 1)
|
|
/* FLAT is a fake segment register (Intel mode). */
|
|
#define RegFlat ((unsigned char) ~0)
|
|
signed char dw2_regnum[2];
|
|
#define Dw2Inval (-1)
|
|
}
|
|
reg_entry;
|
|
|
|
/* Entries in i386_regtab. */
|
|
#define REGNAM_AL 1
|
|
#define REGNAM_AX 25
|
|
#define REGNAM_EAX 41
|
|
|
|
extern const reg_entry i386_regtab[];
|
|
extern const unsigned int i386_regtab_size;
|
|
|
|
typedef struct
|
|
{
|
|
char *seg_name;
|
|
unsigned int seg_prefix;
|
|
}
|
|
seg_entry;
|
|
|
|
extern const seg_entry cs;
|
|
extern const seg_entry ds;
|
|
extern const seg_entry ss;
|
|
extern const seg_entry es;
|
|
extern const seg_entry fs;
|
|
extern const seg_entry gs;
|