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d8740be159
cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
812 lines
28 KiB
Scheme
812 lines
28 KiB
Scheme
;; Linux BPF CPU description -*- Scheme -*-
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;; Copyright (C) 2019 Free Software Foundation, Inc.
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;;
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;; Contributed by Oracle Inc.
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;;
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;; This file is part of the GNU Binutils and of GDB.
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;;
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;; This program is free software; you can redistribute it and/or
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;; modify it under the terms of the GNU General Public License as
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;; published by the Free Software Foundation; either version 3 of the
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;; License, or (at your option) any later version.
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;;
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;; This program is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with this program; if not, write to the Free Software
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;; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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;; 02110-1301, USA.
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;; This file contains a CGEN CPU description for the Linux kernel eBPF
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;; instruction set. eBPF is documented in the linux kernel source
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;; tree. See linux/Documentation/networking/filter.txt, and also the
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;; sources in the networking subsystem, notably
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;; linux/net/core/filter.c.
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(include "simplify.inc")
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(define-arch
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(name bpf)
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(comment "Linux kernel BPF")
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(insn-lsb0? #t)
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;; XXX explain the default-alignment setting is for the simulator.
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;; It is confusing that the simulator follows the emulated memory
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;; access conventions for fetching instructions by pieces...
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(default-alignment unaligned)
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(machs bpf)
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(isas ebpfle ebpfbe))
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;;;; The ISAs
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;; Logically, eBPF comforms a single instruction set featuring two
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;; kind of instructions: 64-bit instructions and 128-bit instructions.
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;;
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;; The 64-bit instructions have the form:
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;;
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;; code:8 regs:8 offset:16 imm:32
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;;
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;; Whereas the 128-bit instructions (at the moment there is only one
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;; of such instructions, lddw) have the form:
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;;
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;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32
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;;
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;; In both formats `regs' is itself composed by two fields:
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;;
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;; dst:4 src:4
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;;
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;; The ISA is supposed to be orthogonal to endianness: the endianness
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;; of the instruction fields follow the endianness of the host running
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;; the eBPF program, and that's all. However, this is not entirely
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;; true. The definition of an eBPF code in the Linux kernel is:
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;;
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;; struct bpf_insn {
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;; __u8 code; /* opcode */
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;; __u8 dst_reg:4; /* dest register */
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;; __u8 src_reg:4; /* source register */
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;; __s16 off; /* signed offset */
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;; __s32 imm; /* signed immediate constant */
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;; };
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;;
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;; Since the ordering of fields in C bitmaps is defined by the
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;; implementation, the impact of endianness in the encoding of eBPF
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;; instructions is effectively defined by GCC. In particular, GCC
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;; places dst_reg before src_reg in little-endian code, and the other
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;; way around in big-endian code.
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;;
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;; So, in reality, eBPF comprises two instruction sets: one for
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;; little-endian with instructions like:
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;;
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;; code:8 src:4 dst:4 offset:16 imm:32 [unused:32 imm:32]
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;;
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;; and another for big-endian with instructions like:
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;;
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;; code:8 dst:4 src:4 offset:16 imm:32 [unused:32 imm:32]
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;;
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;; where `offset' and the immediate fields are encoded in
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;; little-endian and big-endian byte-order, respectively.
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(define-pmacro (define-bpf-isa x-endian)
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(define-isa
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(name (.sym ebpf x-endian))
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(comment "The eBPF instruction set")
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;; Default length to record in ifields. This is used in
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;; calculations involving bit numbers.
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(default-insn-word-bitsize 64)
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;; Length of an unknown instruction. Used by disassembly and by the
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;; simulator's invalid insn handler.
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(default-insn-bitsize 64)
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;; Number of bits of insn that can be initially fetched. This is
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;; the size of the smallest insn.
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(base-insn-bitsize 64)))
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(define-bpf-isa le)
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(define-bpf-isa be)
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(define-pmacro all-isas () (ISA ebpfle,ebpfbe))
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;;;; Hardware Hierarchy
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;;
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;; bpf architecture
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;; |
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;; bpfbf cpu-family
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;; |
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;; bpf machine
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;; |
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;; bpf-def model
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(define-cpu
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(name bpfbf)
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(comment "Linux kernel eBPF virtual CPU")
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(insn-endian big)
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(word-bitsize 64))
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(define-mach
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(name bpf)
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(comment "Linux eBPF")
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(cpu bpfbf)
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(isas ebpfle ebpfbe))
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(define-model
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(name bpf-def)
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(comment "Linux eBPF default model")
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(mach bpf)
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(unit u-exec "execution unit" ()
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1 ; issue
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1 ; done
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() ; state
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() ; inputs
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() ; outputs
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() ; profile action (default)
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))
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;;;; Hardware Elements
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;; eBPF programs can access 10 general-purpose registers which are
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;; 64-bit.
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(define-hardware
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(name h-gpr)
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(comment "General Purpose Registers")
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(attrs all-isas (MACH bpf))
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(type register DI (16))
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(indices keyword "%"
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;; XXX the frame pointer fp is read-only, so it should
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;; go in a different hardware.
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(;; ABI names. Take priority when disassembling.
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(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
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(r7 7) (r8 8) (r9 9) (fp 10)
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;; Additional names recognized when assembling.
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(r0 0) (r6 6) (r10 10))))
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;; The program counter. CGEN requires it, even if it is not visible
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;; to eBPF programs.
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(define-hardware
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(name h-pc)
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(comment "program counter")
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(attrs PC PROFILE all-isas)
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(type pc UDI)
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(get () (raw-reg h-pc))
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(set (newval) (set (raw-reg h-pc) newval)))
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;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
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;; shouldn't be needed, as h-sint is supposed to be able to hold
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;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
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;; in 32-bit hosts. To be fixed in CGEN.
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(dnh h-sint64 "signed 64-bit integer" (all-isas) (immediate DI)
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() () ())
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;;;; The Instruction Sets
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;;; Fields and Opcodes
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;; Convenience macro to shorten the definition of the fields below.
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(define-pmacro (dwf x-name x-comment x-attrs
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x-word-offset x-word-length x-start x-length
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x-mode)
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"Define a field including its containing word."
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(define-ifield
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(name x-name)
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(comment x-comment)
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(.splice attrs (.unsplice x-attrs))
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(word-offset x-word-offset)
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(word-length x-word-length)
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(start x-start)
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(length x-length)
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(mode x-mode)))
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;; For arithmetic and jump instructions the 8-bit code field is
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;; subdivided in:
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;;
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;; op-code:4 op-src:1 op-class:3
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(dwf f-op-code "eBPF opcode code" (all-isas) 0 8 7 4 UINT)
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(dwf f-op-src "eBPF opcode source" (all-isas) 0 8 3 1 UINT)
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(dwf f-op-class "eBPF opcode instruction class" (all-isas) 0 8 2 3 UINT)
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(define-normal-insn-enum insn-op-code-alu "eBPF instruction codes"
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(all-isas) OP_CODE_ f-op-code
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(;; Codes for OP_CLASS_ALU and OP_CLASS_ALU64
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(ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5)
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(LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb)
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(ARSH #xc) (END #xd)
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;; Codes for OP_CLASS_JMP
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(JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4)
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(JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9)
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(JLT #xa) (JLE #xb) (JSLT #xc) (JSLE #xd)))
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(define-normal-insn-enum insn-op-src "eBPF instruction source"
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(all-isas) OP_SRC_ f-op-src
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;; X => use `src' as source operand.
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;; K => use `imm32' as source operand.
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((K #b0) (X #b1)))
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(define-normal-insn-enum insn-op-class "eBPF instruction class"
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(all-isas) OP_CLASS_ f-op-class
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((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
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(ALU #b100) (JMP #b101) (JMP32 #b110) (ALU64 #b111)))
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;; For load/store instructions, the 8-bit code field is subdivided in:
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;;
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;; op-mode:3 op-size:2 op-class:3
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(dwf f-op-mode "eBPF opcode mode" (all-isas) 0 8 7 3 UINT)
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(dwf f-op-size "eBPF opcode size" (all-isas) 0 8 4 2 UINT)
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(define-normal-insn-enum insn-op-mode "eBPF load/store instruction modes"
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(all-isas) OP_MODE_ f-op-mode
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((IMM #b000) (ABS #b001) (IND #b010) (MEM #b011)
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;; #b100 and #b101 are used in classic BPF only, reserved in eBPF.
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(XADD #b110)))
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(define-normal-insn-enum insn-op-size "eBPF load/store instruction sizes"
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(all-isas) OP_SIZE_ f-op-size
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((W #b00) ;; Word: 4 byte
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(H #b01) ;; Half-word: 2 byte
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(B #b10) ;; Byte: 1 byte
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(DW #b11))) ;; Double-word: 8 byte
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;; The fields for the source and destination registers are a bit
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;; tricky. Due to the bizarre nibble swap between little-endian and
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;; big-endian ISAs we need to keep different variants of the fields.
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;;
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;; Note that f-regs is used in the format spec of instructions that do
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;; NOT use registers, where endianness is irrelevant i.e. f-regs is a
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;; constant 0 opcode.
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(dwf f-dstle "eBPF dst register field" ((ISA ebpfle)) 8 8 3 4 UINT)
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(dwf f-srcle "eBPF source register field" ((ISA ebpfle)) 8 8 7 4 UINT)
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(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe)) 8 8 7 4 UINT)
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(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe)) 8 8 3 4 UINT)
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(dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT)
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;; Finally, the fields for the immediates.
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;;
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;; The 16-bit offsets and 32-bit immediates do not present any special
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;; difficulty: we put them in their own instruction word so the
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;; byte-endianness will be properly applied.
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(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 INT)
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(dwf f-imm32 "eBPF 32-bit immediate field" (all-isas) 32 32 31 32 INT)
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;; For the disjoint 64-bit signed immediate, however, we need to use a
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;; multi-ifield.
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(dwf f-imm64-a "eBPF 64-bit immediate a" (all-isas) 32 32 31 32 UINT)
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(dwf f-imm64-b "eBPF 64-bit immediate b" (all-isas) 64 32 31 32 UINT)
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(dwf f-imm64-c "eBPF 64-bit immediate c" (all-isas) 96 32 31 32 UINT)
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(define-multi-ifield
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(name f-imm64)
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(comment "eBPF 64-bit immediate field")
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(attrs all-isas)
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(mode DI)
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(subfields f-imm64-a f-imm64-b f-imm64-c)
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(insert (sequence ()
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(set (ifield f-imm64-b) (const 0))
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(set (ifield f-imm64-c) (srl (ifield f-imm64) (const 32)))
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(set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
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(extract (sequence ()
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(set (ifield f-imm64)
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(or (sll UDI (zext UDI (ifield f-imm64-c)) (const 32))
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(zext UDI (ifield f-imm64-a)))))))
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;;; Operands
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;; A couple of source and destination register operands are defined
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;; for each ISA: ebpfle and ebpfbe.
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(dno dstle "destination register" ((ISA ebpfle)) h-gpr f-dstle)
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(dno srcle "source register" ((ISA ebpfle)) h-gpr f-srcle)
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(dno dstbe "destination register" ((ISA ebpfbe)) h-gpr f-dstbe)
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(dno srcbe "source register" ((ISA ebpfbe)) h-gpr f-srcbe)
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;; Jump instructions have a 16-bit PC-relative address.
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;; CALL instructions have a 32-bit PC-relative address.
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(dno disp16 "16-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
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f-offset16)
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(dno disp32 "32-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
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f-imm32)
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;; Immediate operands in eBPF are signed, and we want the disassembler
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;; to print negative values in a sane way. Therefore we use the macro
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;; below to register a printer, which is itself defined as a C
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;; function in bpf.opc.
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;; define-normal-signed-immediate-operand
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(define-pmacro (dnsio x-name x-comment x-attrs x-type x-index)
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(define-operand
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(name x-name)
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(comment x-comment)
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(.splice attrs (.unsplice x-attrs))
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(type x-type)
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(index x-index)
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(handlers (print "immediate"))))
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(dnsio imm32 "32-bit immediate" (all-isas) h-sint f-imm32)
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(dnsio offset16 "16-bit offset" (all-isas) h-sint f-offset16)
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;; The 64-bit immediate cannot use the default
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;; cgen_parse_signed_integer, because it assumes operands are at much
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;; 32-bit wide. Use our own.
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(define-operand
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(name imm64)
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(comment "64-bit immediate")
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(attrs all-isas)
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(type h-sint64)
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(index f-imm64)
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(handlers (parse "imm64") (print "immediate")))
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;; The endle/endbe instructions take an operand to specify the word
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;; width in endianness conversions. We use both a parser and printer,
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;; which are defined as C functions in bpf.opc.
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(define-operand
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(name endsize)
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(comment "endianness size immediate: 16, 32 or 64")
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(attrs all-isas)
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(type h-uint)
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(index f-imm32)
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(handlers (parse "endsize") (print "endsize")))
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;;; ALU instructions
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;; For each opcode in insn-op-code-alu representing and integer
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;; arithmetic instruction (ADD, SUB, etc) we define a bunch of
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;; instruction variants:
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;;
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;; ADD[32]{i,r}le for the little-endian ISA
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;; ADD[32]{i,r}be for the big-endian ISA
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;;
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;; The `i' variants perform `dst OP imm32 -> dst' operations.
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;; The `r' variants perform `dst OP src -> dst' operations.
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;;
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;; The variants with 32 in their name are of ALU class. Otherwise
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;; they are ALU64 class.
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(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
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x-endian x-mode x-semop)
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(dni (.sym x-basename x-suffix x-endian)
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(.str x-basename x-suffix)
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian)
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(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
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()))
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(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
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x-endian x-mode x-semop)
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(begin
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;; dst = dst OP immediate
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(dni (.sym x-basename x-suffix "i" x-endian)
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(.str x-basename x-suffix " immediate")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$imm32")
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(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
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())
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;; dst = dst OP src
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(dni (.sym x-basename x-suffix "r" x-endian)
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(.str x-basename x-suffix " register")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
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(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
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x-op-class OP_SRC_X x-op-code)
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(set x-mode (.sym dst x-endian)
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(x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
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())))
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(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
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x-endian x-mode)
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(begin
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(dni (.sym mov x-suffix "i" x-endian)
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(.str mov x-suffix " immediate")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$imm32")
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(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
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x-op-class OP_SRC_K x-op-code)
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(set x-mode (.sym dst x-endian) imm32)
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())
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(dni (.sym mov x-suffix "r" x-endian)
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(.str mov x-suffix " register")
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((ISA (.sym ebpf x-endian)))
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(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
|
|
(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
|
|
x-op-class OP_SRC_X x-op-code)
|
|
(set x-mode (.sym dst x-endian) (.sym src x-endian))
|
|
())))
|
|
|
|
|
|
;; Unary ALU instructions (neg)
|
|
(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
|
|
(begin
|
|
(define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
|
|
(define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
|
|
|
|
;; Binary ALU instructions (all the others)
|
|
;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
|
|
(define-pmacro (daib x-basename x-op-code x-endian x-semop)
|
|
(begin
|
|
(define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
|
|
(define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
|
|
|
|
;; Move ALU instructions (mov)
|
|
(define-pmacro (daim x-basename x-op-code x-endian)
|
|
(begin
|
|
(define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
|
|
(define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
|
|
|
|
(define-pmacro (define-alu-instructions x-endian)
|
|
(begin
|
|
(daib add OP_CODE_ADD x-endian add)
|
|
(daib sub OP_CODE_SUB x-endian sub)
|
|
(daib mul OP_CODE_MUL x-endian mul)
|
|
(daib div OP_CODE_DIV x-endian div)
|
|
(daib or OP_CODE_OR x-endian or)
|
|
(daib and OP_CODE_AND x-endian and)
|
|
(daib lsh OP_CODE_LSH x-endian sll)
|
|
(daib rsh OP_CODE_RSH x-endian srl)
|
|
(daib mod OP_CODE_MOD x-endian mod)
|
|
(daib xor OP_CODE_XOR x-endian xor)
|
|
(daib arsh OP_CODE_ARSH x-endian sra)
|
|
(daiu neg OP_CODE_NEG x-endian neg)
|
|
(daim mov OP_CODE_MOV x-endian)))
|
|
|
|
(define-alu-instructions le)
|
|
(define-alu-instructions be)
|
|
|
|
;;; Endianness conversion instructions
|
|
|
|
;; The endianness conversion instructions come in several variants:
|
|
;;
|
|
;; END{le,be}le for the little-endian ISA
|
|
;; END{le,be}be for the big-endian ISA
|
|
;;
|
|
;; Please do not be confused by the repeated `be' and `le' here. Each
|
|
;; ISA has both endle and endbe instructions. It is the disposition
|
|
;; of the source and destination register fields that change between
|
|
;; ISAs, not the semantics of the instructions themselves (see section
|
|
;; "The ISAs" above in this very file.)
|
|
|
|
(define-pmacro (define-endian-insn x-suffix x-op-src x-endian)
|
|
(dni (.sym "end" x-suffix x-endian)
|
|
(.str "end" x-suffix " register")
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "end" x-suffix " $dst" x-endian ",$endsize")
|
|
(+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
|
|
OP_CLASS_ALU x-op-src OP_CODE_END)
|
|
(set (.sym dst x-endian)
|
|
(c-call DI "bpfbf_end" (.sym dst x-endian) endsize))
|
|
()))
|
|
|
|
(define-endian-insn "le" OP_SRC_K le)
|
|
(define-endian-insn "be" OP_SRC_X le)
|
|
(define-endian-insn "le" OP_SRC_K be)
|
|
(define-endian-insn "be" OP_SRC_X be)
|
|
|
|
;;; Load/Store instructions
|
|
|
|
;; The lddw instruction takes a 64-bit immediate as an operand. Since
|
|
;; this instruction also takes a `dst' operand, we need to define a
|
|
;; variant for each ISA:
|
|
;;
|
|
;; LDDWle for the little-endian ISA
|
|
;; LDDWbe for the big-endian ISA
|
|
|
|
(define-pmacro (define-lddw x-endian)
|
|
(dni (.sym lddw x-endian)
|
|
(.str "lddw" x-endian)
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "lddw $dst" x-endian ",$imm64")
|
|
(+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
|
|
(.sym dst x-endian)
|
|
OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
|
|
(set DI (.sym dst x-endian) imm64)
|
|
()))
|
|
|
|
(define-lddw le)
|
|
(define-lddw be)
|
|
|
|
;; The absolute load instructions are non-generic loads designed to be
|
|
;; used in socket filters. They come in several variants:
|
|
;;
|
|
;; LDABS{w,h,b,dw}
|
|
|
|
(define-pmacro (dlabs x-suffix x-size x-smode)
|
|
(dni (.sym "ldabs" x-suffix)
|
|
(.str "ldabs" x-suffix)
|
|
(all-isas)
|
|
(.str "ldabs" x-suffix " $imm32")
|
|
(+ imm32 (f-offset16 0) (f-regs 0)
|
|
OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
|
|
(set x-smode
|
|
(reg x-smode h-gpr 0)
|
|
(mem x-smode
|
|
(add DI
|
|
(mem DI
|
|
(add DI
|
|
(reg DI h-gpr 6) ;; Pointer to struct sk_buff
|
|
(const DI 0))) ;; XXX offsetof
|
|
;; (struct sk_buff, data) XXX but the offset
|
|
;; depends on CONFIG_* options, so this should
|
|
;; be configured in the simulator and driven by
|
|
;; command-line options. Handle with a c-call.
|
|
imm32)))
|
|
;; XXX this clobbers R1-R5
|
|
()))
|
|
|
|
(dlabs "w" W SI)
|
|
(dlabs "h" H HI)
|
|
(dlabs "b" B QI)
|
|
(dlabs "dw" DW DI)
|
|
|
|
;; The indirect load instructions are non-generic loads designed to be
|
|
;; used in socket filters. They come in several variants:
|
|
;;
|
|
;; LDIND{w,h,b,dw}le for the little-endian ISA
|
|
;; LDIND[w,h,b,dw}be for the big-endian ISA
|
|
|
|
(define-pmacro (dlind x-suffix x-size x-endian x-smode)
|
|
(dni (.sym "ldind" x-suffix x-endian)
|
|
(.str "ldind" x-suffix)
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "ldind" x-suffix " $src" x-endian ",$imm32")
|
|
(+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
|
|
OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
|
|
(set x-smode
|
|
(reg x-smode h-gpr 0)
|
|
(mem x-smode
|
|
(add DI
|
|
(mem DI
|
|
(add DI
|
|
(reg DI h-gpr 6) ;; Pointer to struct sk_buff
|
|
(const DI 0))) ;; XXX offsetof
|
|
;; (struct sk_buff, data) XXX but the offset
|
|
;; depends on CONFIG_* options, so this should
|
|
;; be configured in the simulator and driven by
|
|
;; command-line options. Handle with a c-call.
|
|
(add DI
|
|
(.sym src x-endian)
|
|
imm32))))
|
|
;; XXX this clobbers R1-R5
|
|
()))
|
|
|
|
(define-pmacro (define-ldind x-endian)
|
|
(begin
|
|
(dlind "w" W x-endian SI)
|
|
(dlind "h" H x-endian HI)
|
|
(dlind "b" B x-endian QI)
|
|
(dlind "dw" DW x-endian DI)))
|
|
|
|
(define-ldind le)
|
|
(define-ldind be)
|
|
|
|
;; Generic load and store instructions are provided for several word
|
|
;; sizes. They come in several variants:
|
|
;;
|
|
;; LDX{b,h,w,dw}le, STX{b,h,w,dw}le for the little-endian ISA
|
|
;;
|
|
;; LDX{b,h,w,dw}be, STX{b,h,w,dw}be for the big-endian ISA
|
|
;;
|
|
;; Loads operate on [$SRC+-OFFSET] -> $DST
|
|
;; Stores operate on $SRC -> [$DST+-OFFSET]
|
|
|
|
(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
|
|
(dni (.sym x-basename x-suffix x-endian)
|
|
(.str x-basename x-suffix)
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
|
|
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
|
|
OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
|
|
(set x-mode
|
|
(.sym dst x-endian)
|
|
(mem x-mode (add DI (.sym src x-endian) (ext DI (trunc HI offset16)))))
|
|
()))
|
|
|
|
(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
|
|
(dni (.sym x-basename x-suffix x-endian)
|
|
(.str x-basename x-suffix)
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
|
|
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
|
|
OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
|
|
(set x-mode
|
|
(mem x-mode (add DI (.sym dst x-endian) (ext DI (trunc HI offset16))))
|
|
(.sym src x-endian)) ;; XXX address is section-relative
|
|
()))
|
|
|
|
(define-pmacro (define-ldstx-insns x-endian)
|
|
(begin
|
|
(dxli "ldx" "w" W x-endian SI)
|
|
(dxli "ldx" "h" H x-endian HI)
|
|
(dxli "ldx" "b" B x-endian QI)
|
|
(dxli "ldx" "dw" DW x-endian DI)
|
|
|
|
(dxsi "stx" "w" W x-endian SI)
|
|
(dxsi "stx" "h" H x-endian HI)
|
|
(dxsi "stx" "b" B x-endian QI)
|
|
(dxsi "stx" "dw" DW x-endian DI)))
|
|
|
|
(define-ldstx-insns le)
|
|
(define-ldstx-insns be)
|
|
|
|
;; Generic store instructions of the form IMM32 -> [$DST+OFFSET] are
|
|
;; provided in several variants:
|
|
;;
|
|
;; ST{b,h,w,dw}le for the little-endian ISA
|
|
;; ST{b,h,w,dw}be for the big-endian ISA
|
|
|
|
(define-pmacro (dsti x-suffix x-size x-endian x-mode)
|
|
(dni (.sym "st" x-suffix x-endian)
|
|
(.str "st" x-suffix)
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
|
|
(+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
|
|
OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
|
|
(set x-mode
|
|
(mem x-mode (add DI (.sym dst x-endian) offset16))
|
|
imm32) ;; XXX address is section-relative
|
|
()))
|
|
|
|
(define-pmacro (define-st-insns x-endian)
|
|
(begin
|
|
(dsti "b" B x-endian QI)
|
|
(dsti "h" H x-endian HI)
|
|
(dsti "w" W x-endian SI)
|
|
(dsti "dw" DW x-endian DI)))
|
|
|
|
(define-st-insns le)
|
|
(define-st-insns be)
|
|
|
|
;;; Jump instructions
|
|
|
|
;; Compare-and-jump instructions, on the other hand, make use of
|
|
;; registers. Therefore, we need to define several variants in both
|
|
;; ISAs:
|
|
;;
|
|
;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
|
|
;; little-endian ISA.
|
|
;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
|
|
;; big-endian ISA.
|
|
|
|
(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
|
|
(begin
|
|
(dni (.sym j x-cond x-suffix i x-endian)
|
|
(.str j x-cond x-suffix " i")
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
|
|
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
|
|
x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
|
|
(if VOID (x-semop x-mode (.sym dst x-endian) imm32)
|
|
(set DI
|
|
(reg DI h-pc) (add DI (reg DI h-pc)
|
|
(mul DI (add HI disp16 1) 8))))
|
|
())
|
|
(dni (.sym j x-cond x-suffix r x-endian)
|
|
(.str j x-cond x-suffix " r")
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
|
|
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
|
|
x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
|
|
(if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
|
|
(set DI
|
|
(reg DI h-pc) (add DI (reg DI h-pc)
|
|
(mul DI (add HI disp16 1) 8))))
|
|
())))
|
|
|
|
(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
|
|
(begin
|
|
(define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
|
|
(define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
|
|
|
|
(define-pmacro (define-condjump-insns x-endian)
|
|
(begin
|
|
(dcji "eq" JEQ x-endian eq)
|
|
(dcji "gt" JGT x-endian gtu)
|
|
(dcji "ge" JGE x-endian geu)
|
|
(dcji "lt" JLT x-endian ltu)
|
|
(dcji "le" JLE x-endian leu)
|
|
(dcji "set" JSET x-endian and)
|
|
(dcji "ne" JNE x-endian ne)
|
|
(dcji "sgt" JSGT x-endian gt)
|
|
(dcji "sge" JSGE x-endian ge)
|
|
(dcji "slt" JSLT x-endian lt)
|
|
(dcji "sle" JSLE x-endian le)))
|
|
|
|
(define-condjump-insns le)
|
|
(define-condjump-insns be)
|
|
|
|
;; The `call' instruction doesn't make use of registers, but the
|
|
;; semantic routine should have access to the src register in order to
|
|
;; properly interpret the meaning of disp32. Therefore we need one
|
|
;; version per ISA.
|
|
|
|
(define-pmacro (define-call-insn x-endian)
|
|
(dni (.sym call x-endian)
|
|
"call"
|
|
((ISA (.sym ebpf x-endian)))
|
|
"call $disp32"
|
|
(+ disp32 (f-offset16 0) (f-regs 0)
|
|
OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
|
|
(c-call VOID
|
|
"bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
|
|
()))
|
|
|
|
(define-call-insn le)
|
|
(define-call-insn be)
|
|
|
|
;; The jump-always and `exit' instructions dont make use of either
|
|
;; source nor destination registers, so only one variant per
|
|
;; instruction is defined.
|
|
|
|
(dni ja "ja" (all-isas) "ja $disp16"
|
|
(+ (f-imm32 0) disp16 (f-regs 0)
|
|
OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
|
|
(set DI (reg DI h-pc) (add DI (reg DI h-pc)
|
|
(mul DI (add HI disp16 1) 8)))
|
|
())
|
|
|
|
(dni "exit" "exit" (all-isas) "exit"
|
|
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
|
|
OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
|
|
(c-call VOID "bpfbf_exit")
|
|
())
|
|
|
|
;;; Atomic instructions
|
|
|
|
;; The atomic exchange-and-add instructions come in two flavors: one
|
|
;; for swapping 64-bit quantities and another for 32-bit quantities.
|
|
|
|
(define-pmacro (sem-exchange-and-add x-endian x-mode)
|
|
(sequence VOID ((x-mode tmp))
|
|
;; XXX acquire lock in simulator... as a hardware element?
|
|
(set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
|
|
(set x-mode
|
|
(mem x-mode (add DI (.sym dst x-endian) offset16))
|
|
(add x-mode tmp (.sym src x-endian)))))
|
|
|
|
(define-pmacro (define-atomic-insns x-endian)
|
|
(begin
|
|
(dni (.str "xadddw" x-endian)
|
|
"xadddw"
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
|
|
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
|
|
offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
|
|
(sem-exchange-and-add x-endian DI)
|
|
())
|
|
(dni (.str "xaddw" x-endian)
|
|
"xaddw"
|
|
((ISA (.sym ebpf x-endian)))
|
|
(.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
|
|
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
|
|
offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
|
|
(sem-exchange-and-add x-endian SI)
|
|
())))
|
|
|
|
(define-atomic-insns le)
|
|
(define-atomic-insns be)
|
|
|
|
;;; Breakpoint instruction
|
|
|
|
;; The brkpt instruction is used by the BPF simulator and it doesn't
|
|
;; really belong to the eBPF instruction set.
|
|
|
|
(dni "brkpt" "brkpt" (all-isas) "brkpt"
|
|
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
|
|
OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
|
|
(c-call VOID "bpfbf_breakpoint")
|
|
())
|