mirror of
https://sourceware.org/git/binutils-gdb.git
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55552082e8
arch.c: Regenerate.
arch.h: Regenerate.
cpu.c: Regenerate.
cpu.h: Regenerate.
cpuall.h: Regenerate.
cpux.c: Regenerate.
cpux.h: Regenerate.
decode.c: Regenerate.
decode.h: Regenerate.
decodex.c: Regenerate.
decodex.h: Regenerate.
model.c: Regenerate.
modelx.c: Regenerate.
sem-switch.c: Regenerate.
sem.c: Regenerate.
semx-switch.c: Regenerate.
2516 lines
62 KiB
C
2516 lines
62 KiB
C
/* Simulator instruction semantics for m32rbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifdef DEFINE_LABELS
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/* The labels have the case they have because the enum of insn types
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is all uppercase and in the non-stdc case the insn symbol is built
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into the enum name. */
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static struct {
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int index;
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void *label;
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} labels[] = {
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{ M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
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{ M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
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{ M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
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{ M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
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{ M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
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{ M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
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{ M32RBF_INSN_ADD, && case_sem_INSN_ADD },
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{ M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
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{ M32RBF_INSN_AND, && case_sem_INSN_AND },
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{ M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
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{ M32RBF_INSN_OR, && case_sem_INSN_OR },
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{ M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
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{ M32RBF_INSN_XOR, && case_sem_INSN_XOR },
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{ M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
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{ M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
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{ M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
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{ M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
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{ M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
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{ M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
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{ M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
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{ M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
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{ M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
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{ M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
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{ M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
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{ M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
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{ M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
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{ M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
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{ M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
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{ M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
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{ M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
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{ M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
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{ M32RBF_INSN_BNE, && case_sem_INSN_BNE },
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{ M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
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{ M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
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{ M32RBF_INSN_CMP, && case_sem_INSN_CMP },
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{ M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
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{ M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
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{ M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
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{ M32RBF_INSN_DIV, && case_sem_INSN_DIV },
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{ M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
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{ M32RBF_INSN_REM, && case_sem_INSN_REM },
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{ M32RBF_INSN_REMU, && case_sem_INSN_REMU },
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{ M32RBF_INSN_JL, && case_sem_INSN_JL },
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{ M32RBF_INSN_JMP, && case_sem_INSN_JMP },
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{ M32RBF_INSN_LD, && case_sem_INSN_LD },
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{ M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
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{ M32RBF_INSN_LDB, && case_sem_INSN_LDB },
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{ M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
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{ M32RBF_INSN_LDH, && case_sem_INSN_LDH },
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{ M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
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{ M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
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{ M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
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{ M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
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{ M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
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{ M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
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{ M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
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{ M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
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{ M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
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{ M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
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{ M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
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{ M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
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{ M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
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{ M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
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{ M32RBF_INSN_MUL, && case_sem_INSN_MUL },
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{ M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
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{ M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
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{ M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
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{ M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
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{ M32RBF_INSN_MV, && case_sem_INSN_MV },
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{ M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
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{ M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
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{ M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
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{ M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
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{ M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
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{ M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
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{ M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
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{ M32RBF_INSN_NEG, && case_sem_INSN_NEG },
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{ M32RBF_INSN_NOP, && case_sem_INSN_NOP },
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{ M32RBF_INSN_NOT, && case_sem_INSN_NOT },
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{ M32RBF_INSN_RAC, && case_sem_INSN_RAC },
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{ M32RBF_INSN_RACH, && case_sem_INSN_RACH },
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{ M32RBF_INSN_RTE, && case_sem_INSN_RTE },
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{ M32RBF_INSN_SETH, && case_sem_INSN_SETH },
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{ M32RBF_INSN_SLL, && case_sem_INSN_SLL },
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{ M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
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{ M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
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{ M32RBF_INSN_SRA, && case_sem_INSN_SRA },
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{ M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
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{ M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
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{ M32RBF_INSN_SRL, && case_sem_INSN_SRL },
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{ M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
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{ M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
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{ M32RBF_INSN_ST, && case_sem_INSN_ST },
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{ M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
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{ M32RBF_INSN_STB, && case_sem_INSN_STB },
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{ M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
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{ M32RBF_INSN_STH, && case_sem_INSN_STH },
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{ M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
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{ M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
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{ M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
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{ M32RBF_INSN_SUB, && case_sem_INSN_SUB },
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{ M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
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{ M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
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{ M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
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{ M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
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{ 0, 0 }
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};
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int i;
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for (i = 0; labels[i].label != 0; ++i)
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{
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#if FAST_P
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CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
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#else
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CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
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#endif
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}
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#undef DEFINE_LABELS
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#endif /* DEFINE_LABELS */
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#ifdef DEFINE_SWITCH
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/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
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off frills like tracing and profiling. */
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/* FIXME: A better way would be to have TRACE_RESULT check for something
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that can cause it to be optimized out. Another way would be to emit
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special handlers into the instruction "stream". */
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#if FAST_P
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#undef TRACE_RESULT
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#define TRACE_RESULT(cpu, abuf, name, type, val)
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#endif
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#undef GET_ATTR
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
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#else
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#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
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#endif
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{
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#if WITH_SCACHE_PBB
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/* Branch to next handler without going around main loop. */
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#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
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SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
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#else /* ! WITH_SCACHE_PBB */
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#define NEXT(vpc) BREAK (sem)
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#ifdef __GNUC__
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#if FAST_P
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SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
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#else
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SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
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#endif
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#else
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SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
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#endif
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#endif /* ! WITH_SCACHE_PBB */
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{
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CASE (sem, INSN_X_INVALID) : /* --invalid-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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/* Update the recorded pc in the cpu state struct.
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Only necessary for WITH_SCACHE case, but to avoid the
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conditional compilation .... */
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SET_H_PC (pc);
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/* Virtual insns have zero size. Overwrite vpc with address of next insn
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using the default-insn-bitsize spec. When executing insns in parallel
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we may want to queue the fault and continue execution. */
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vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
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vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_X_AFTER) : /* --after-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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#if WITH_SCACHE_PBB_M32RBF
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m32rbf_pbb_after (current_cpu, sem_arg);
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#endif
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_X_BEFORE) : /* --before-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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#if WITH_SCACHE_PBB_M32RBF
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m32rbf_pbb_before (current_cpu, sem_arg);
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#endif
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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#if WITH_SCACHE_PBB_M32RBF
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#ifdef DEFINE_SWITCH
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vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
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pbb_br_type, pbb_br_npc);
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BREAK (sem);
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#else
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/* FIXME: Allow provision of explicit ifmt spec in insn spec. */
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vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
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CPU_PBB_BR_TYPE (current_cpu),
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CPU_PBB_BR_NPC (current_cpu));
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#endif
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#endif
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_X_CHAIN) : /* --chain-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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#if WITH_SCACHE_PBB_M32RBF
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vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
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#ifdef DEFINE_SWITCH
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BREAK (sem);
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#endif
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#endif
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_X_BEGIN) : /* --begin-- */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.fmt_empty.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
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{
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#if WITH_SCACHE_PBB_M32RBF
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#if defined DEFINE_SWITCH || defined FAST_P
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/* In the switch case FAST_P is a constant, allowing several optimizations
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in any called inline functions. */
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vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
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#else
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#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
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vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
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#else
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vpc = m32rbf_pbb_begin (current_cpu, 0);
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#endif
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#endif
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#endif
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_ADD) : /* add $dr,$sr */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.sfmt_add.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
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{
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SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
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* FLD (i_dr) = opval;
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TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
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{
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SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
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ARGBUF *abuf = SEM_ARGBUF (sem_arg);
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#define FLD(f) abuf->fields.sfmt_add3.f
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int UNUSED written = 0;
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IADDR UNUSED pc = abuf->addr;
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vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
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{
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SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
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* FLD (i_dr) = opval;
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TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
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}
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#undef FLD
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}
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NEXT (vpc);
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CASE (sem, INSN_AND) : /* and $dr,$sr */
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{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_and3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_OR) : /* or $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_and3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_XOR) : /* xor $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_and3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_addi.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;BI temp1;
|
|
temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
|
|
temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
BI opval = temp1;
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI temp0;BI temp1;
|
|
temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
|
|
temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
BI opval = temp1;
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;BI temp1;
|
|
temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
|
|
temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
BI opval = temp1;
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BC8) : /* bc.s $disp8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl8.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
if (CPU (h_cond)) {
|
|
{
|
|
USI opval = FLD (i_disp8);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BC24) : /* bc.l $disp24 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl24.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (CPU (h_cond)) {
|
|
{
|
|
USI opval = FLD (i_disp24);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 3);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (EQSI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (GESI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (GTSI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (LESI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (LTSI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_src2), 0)) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BL8) : /* bl.s $disp8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl8.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
{
|
|
SI opval = ADDSI (ANDSI (pc, -4), 4);
|
|
CPU (h_gr[((UINT) 14)]) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
USI opval = FLD (i_disp8);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BL24) : /* bl.l $disp24 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl24.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
{
|
|
SI opval = ADDSI (pc, 4);
|
|
CPU (h_gr[((UINT) 14)]) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
USI opval = FLD (i_disp24);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl8.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
if (NOTBI (CPU (h_cond))) {
|
|
{
|
|
USI opval = FLD (i_disp8);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl24.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NOTBI (CPU (h_cond))) {
|
|
{
|
|
USI opval = FLD (i_disp24);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_beq.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_src1), * FLD (i_src2))) {
|
|
{
|
|
USI opval = FLD (i_disp16);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
written |= (1 << 3);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl8.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
USI opval = FLD (i_disp8);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_bl24.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
USI opval = FLD (i_disp24);
|
|
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_d.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_d.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_DIV) : /* div $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_sr), 0)) {
|
|
{
|
|
SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_sr), 0)) {
|
|
{
|
|
SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_REM) : /* rem $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_sr), 0)) {
|
|
{
|
|
SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_REMU) : /* remu $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
if (NESI (* FLD (i_sr), 0)) {
|
|
{
|
|
SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
written |= (1 << 2);
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_JL) : /* jl $sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_jl.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;USI temp1;
|
|
temp0 = ADDSI (ANDSI (pc, -4), 4);
|
|
temp1 = ANDSI (* FLD (i_sr), -4);
|
|
{
|
|
SI opval = temp0;
|
|
CPU (h_gr[((UINT) 14)]) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
USI opval = temp1;
|
|
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_JMP) : /* jmp $sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_jl.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
USI opval = ANDSI (* FLD (i_sr), -4);
|
|
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LD) : /* ld $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;SI temp1;
|
|
temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
|
|
temp1 = ADDSI (* FLD (i_sr), 4);
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
SI opval = temp1;
|
|
* FLD (i_sr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld24.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = FLD (i_uimm24);
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_addi.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = FLD (f_simm8);
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = FLD (f_simm16);
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
{
|
|
BI opval = 1;
|
|
CPU (h_lock) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
|
|
}
|
|
{
|
|
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MUL) : /* mul $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MV) : /* mv $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = * FLD (i_sr);
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_seth.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_seth.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = TRUNCDISI (GET_H_ACCUM ());
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_seth.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = GET_H_CR (FLD (f_r2));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
USI opval = * FLD (i_sr);
|
|
SET_H_CR (FLD (f_r1), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_NEG) : /* neg $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = NEGSI (* FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_NOP) : /* nop */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.fmt_empty.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_NOT) : /* not $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_ld_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = INVSI (* FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_RAC) : /* rac */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.fmt_empty.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI tmp_tmp1;
|
|
tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
|
|
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
|
|
{
|
|
DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_RACH) : /* rach */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.fmt_empty.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
DI tmp_tmp1;
|
|
tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
|
|
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
|
|
tmp_tmp1 = MAKEDI (16383, 0x80000000);
|
|
} else {
|
|
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
|
|
tmp_tmp1 = MAKEDI (16760832, 0);
|
|
} else {
|
|
tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
|
|
}
|
|
}
|
|
tmp_tmp1 = SLLDI (tmp_tmp1, 1);
|
|
{
|
|
DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
|
|
SET_H_ACCUM (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_RTE) : /* rte */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.fmt_empty.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
{
|
|
USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
|
|
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
{
|
|
USI opval = GET_H_CR (((UINT) 14));
|
|
SET_H_CR (((UINT) 6), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
|
|
}
|
|
{
|
|
UQI opval = CPU (h_bpsw);
|
|
SET_H_PSW (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
|
|
}
|
|
{
|
|
UQI opval = CPU (h_bbpsw);
|
|
CPU (h_bpsw) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
|
|
}
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_seth.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = SLLSI (FLD (f_hi16), 16);
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SLL) : /* sll $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_slli.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRA) : /* sra $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_slli.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRL) : /* srl $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add3.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_slli.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ST) : /* st $src1,@$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = * FLD (i_src1);
|
|
SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_d.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
SI opval = * FLD (i_src1);
|
|
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
QI opval = * FLD (i_src1);
|
|
SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_d.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
QI opval = * FLD (i_src1);
|
|
SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
HI opval = * FLD (i_src1);
|
|
SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_d.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
|
|
|
{
|
|
HI opval = * FLD (i_src1);
|
|
SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI tmp_new_src2;
|
|
tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
|
|
{
|
|
SI opval = * FLD (i_src1);
|
|
SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
{
|
|
SI opval = tmp_new_src2;
|
|
* FLD (i_src2) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI tmp_new_src2;
|
|
tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
|
|
{
|
|
SI opval = * FLD (i_src1);
|
|
SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
{
|
|
SI opval = tmp_new_src2;
|
|
* FLD (i_src2) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SUB) : /* sub $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;BI temp1;
|
|
temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
|
|
temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
BI opval = temp1;
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_add.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
SI temp0;BI temp1;
|
|
temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
|
|
temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
|
|
{
|
|
SI opval = temp0;
|
|
* FLD (i_dr) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
|
|
}
|
|
{
|
|
BI opval = temp1;
|
|
CPU (h_cond) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
|
|
}
|
|
}
|
|
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_TRAP) : /* trap $uimm4 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_trap.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
SEM_BRANCH_INIT
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
{
|
|
USI opval = GET_H_CR (((UINT) 6));
|
|
SET_H_CR (((UINT) 14), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
|
|
}
|
|
{
|
|
USI opval = ADDSI (pc, 4);
|
|
SET_H_CR (((UINT) 6), opval);
|
|
TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
|
|
}
|
|
{
|
|
UQI opval = CPU (h_bpsw);
|
|
CPU (h_bbpsw) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
|
|
}
|
|
{
|
|
UQI opval = GET_H_PSW ();
|
|
CPU (h_bpsw) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
|
|
}
|
|
{
|
|
UQI opval = ANDQI (GET_H_PSW (), 128);
|
|
SET_H_PSW (opval);
|
|
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
|
|
}
|
|
{
|
|
SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
|
|
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
|
|
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
|
|
}
|
|
}
|
|
|
|
SEM_BRANCH_FINI (vpc);
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
|
|
{
|
|
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
|
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
|
#define FLD(f) abuf->fields.sfmt_st_plus.f
|
|
int UNUSED written = 0;
|
|
IADDR UNUSED pc = abuf->addr;
|
|
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
|
|
|
{
|
|
if (CPU (h_lock)) {
|
|
{
|
|
SI opval = * FLD (i_src1);
|
|
SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
|
|
written |= (1 << 4);
|
|
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
|
|
}
|
|
}
|
|
{
|
|
BI opval = 0;
|
|
CPU (h_lock) = opval;
|
|
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
|
|
}
|
|
}
|
|
|
|
abuf->written = written;
|
|
#undef FLD
|
|
}
|
|
NEXT (vpc);
|
|
|
|
|
|
}
|
|
ENDSWITCH (sem) /* End of semantic switch. */
|
|
|
|
/* At this point `vpc' contains the next insn to execute. */
|
|
}
|
|
|
|
#undef DEFINE_SWITCH
|
|
#endif /* DEFINE_SWITCH */
|