Jeff Law 477904ca75 Fix for v850e divq instruction ... This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch.		2022-04-06 11:10:40 -04:00
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aarch64
arm	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
avr
bfin
bpf
common	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
cr16
cris	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
d10v
erc32	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
example-synacor
frv
ft32
h8300
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iq2000
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m68hc11
mcore
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mips
mn10300
moxie
msp430
or1k
ppc
pru
riscv
rl78	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
rx	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
sh
testsuite	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
v850	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
.gitignore
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arch-subdir.mk.in
ChangeLog-2021
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configure	sim: add arch/.gdbinit stub scripts	2022-03-28 23:10:34 -04:00
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Makefile.in	sim: add arch/.gdbinit stub scripts	2022-03-28 23:10:34 -04:00
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