mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-09 04:21:49 +08:00
471 lines
10 KiB
C
471 lines
10 KiB
C
#define WITH_CORE
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#define WITH_MODULO_MEMORY 1
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#define WITH_WATCHPOINTS 1
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#define WITH_TARGET_WORD_MSB 31
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#include "sim-basics.h"
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#include <signal.h>
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typedef address_word sim_cia;
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/* This simulator doesn't cache state */
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#define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
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#define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
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/* Get the number of instructions. FIXME: must be a more elegant way
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of doing this. */
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#include "itable.h"
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#define MAX_INSNS (nr_itable_entries)
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#define INSN_NAME(i) itable[(i)].name
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#include "sim-base.h"
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#include "simops.h"
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#include "bfd.h"
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typedef signed8 int8;
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typedef unsigned8 uint8;
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typedef signed16 int16;
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typedef unsigned16 uint16;
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typedef signed32 int32;
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typedef unsigned32 uint32;
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typedef unsigned32 reg_t;
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/* The current state of the processor; registers, memory, etc. */
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typedef struct _v850_regs {
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reg_t regs[32]; /* general-purpose registers */
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reg_t sregs[32]; /* system registers, including psw */
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reg_t pc;
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int dummy_mem; /* where invalid accesses go */
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} v850_regs;
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struct _sim_cpu
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{
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/* ... simulator specific members ... */
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v850_regs reg;
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reg_t psw_mask; /* only allow non-reserved bits to be set */
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sim_event *pending_nmi;
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/* ... base type ... */
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sim_cpu_base base;
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};
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#define CPU_CIA(CPU) ((CPU)->reg.pc)
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struct sim_state {
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sim_cpu cpu[MAX_NR_PROCESSORS];
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#if (WITH_SMP)
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#define STATE_CPU(sd,n) (&(sd)->cpu[n])
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#else
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#define STATE_CPU(sd,n) (&(sd)->cpu[0])
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#endif
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#if 0
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SIM_ADDR rom_size;
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SIM_ADDR low_end;
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SIM_ADDR high_start;
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SIM_ADDR high_base;
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void *mem;
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#endif
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sim_state_base base;
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};
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/* For compatibility, until all functions converted to passing
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SIM_DESC as an argument */
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extern SIM_DESC simulator;
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#define V850_ROM_SIZE 0x8000
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#define V850_LOW_END 0x200000
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#define V850_HIGH_START 0xffe000
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#define SIG_V850_EXIT -1 /* indication of a normal exit */
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/* Because we are still using the old semantic table, provide compat
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macro's that store the instruction where the old simops expects
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it. */
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extern uint32 OP[4];
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#if 0
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OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
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OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
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OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
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OP[3] = inst;
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#endif
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#define SAVE_1 \
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PC = cia; \
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OP[0] = instruction_0 & 0x1f; \
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OP[1] = (instruction_0 >> 11) & 0x1f; \
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OP[2] = 0; \
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OP[3] = instruction_0
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#define COMPAT_1(CALL) \
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SAVE_1; \
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PC += (CALL); \
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nia = PC
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#define SAVE_2 \
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PC = cia; \
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OP[0] = instruction_0 & 0x1f; \
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OP[1] = (instruction_0 >> 11) & 0x1f; \
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OP[2] = instruction_1; \
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OP[3] = (instruction_1 << 16) | instruction_0
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#define COMPAT_2(CALL) \
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SAVE_2; \
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PC += (CALL); \
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nia = PC
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/* new */
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#define GR ((CPU)->reg.regs)
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#define SR ((CPU)->reg.sregs)
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/* old */
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#define State (STATE_CPU (simulator, 0)->reg)
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#define PC (State.pc)
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#define SP (State.regs[3])
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#define EP (State.regs[30])
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#define EIPC (State.sregs[0])
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#define EIPSW (State.sregs[1])
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#define FEPC (State.sregs[2])
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#define FEPSW (State.sregs[3])
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#define ECR (State.sregs[4])
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#define PSW (State.sregs[5])
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/* start-sanitize-v850e */
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#define CTPC (SR[16])
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#define CTPSW (SR[17])
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/* end-sanitize-v850e */
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#define DBPC (State.sregs[18])
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#define DBPSW (State.sregs[19])
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/* start-sanitize-v850e */
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#define CTBP (State.sregs[20])
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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#define PSW_US BIT32 (8)
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/* end-sanitize-v850eq */
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#define PSW_NP 0x80
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#define PSW_EP 0x40
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#define PSW_ID 0x20
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#define PSW_SAT 0x10
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#define PSW_CY 0x8
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#define PSW_OV 0x4
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#define PSW_S 0x2
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#define PSW_Z 0x1
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
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/* sign-extend a 5-bit number */
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#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
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/* sign-extend a 9-bit number */
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#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
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^ (~UNSIGNED64 (0x7fffffffff))) \
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+ UNSIGNED64 (0x8000000000))
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
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^ (~ UNSIGNED64 (0x7ffffffffff))) \
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+ UNSIGNED64 (0x80000000000))
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
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^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
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+ UNSIGNED64 (0x800000000000000))
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/* No sign extension */
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#define NOP(x) (x)
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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#define RLW(x) load_mem (x, 4)
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#ifdef _WIN32
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#ifndef SIGTRAP
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#define SIGTRAP 5
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#endif
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#ifndef SIGQUIT
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#define SIGQUIT 3
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#endif
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#endif
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/* Function declarations. */
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#define IMEM(EA) \
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sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
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PC, sim_core_execute_map, (EA))
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#define IMEM_IMMED(EA,N) \
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sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
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PC, sim_core_execute_map, (EA) + (N) * 2)
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#define load_mem(ADDR,LEN) \
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sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
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PC, sim_core_read_map, (ADDR))
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#define store_mem(ADDR,LEN,DATA) \
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sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
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PC, sim_core_write_map, (ADDR), (DATA))
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/* compare cccc field against PSW */
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int condition_met (unsigned code);
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/* Debug/tracing calls */
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enum op_types
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{
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OP_UNKNOWN,
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OP_NONE,
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OP_TRAP,
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OP_REG,
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OP_REG_REG,
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OP_REG_REG_CMP,
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OP_REG_REG_MOVE,
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OP_IMM_REG,
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OP_IMM_REG_CMP,
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OP_IMM_REG_MOVE,
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OP_COND_BR,
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OP_LOAD16,
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OP_STORE16,
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OP_LOAD32,
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OP_STORE32,
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OP_JUMP,
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OP_IMM_REG_REG,
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OP_UIMM_REG_REG,
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OP_IMM16_REG_REG,
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OP_UIMM16_REG_REG,
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OP_BIT,
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OP_EX1,
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OP_EX2,
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OP_LDSR,
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OP_STSR,
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/* start-sanitize-v850e */
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OP_BIT_CHANGE,
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OP_REG_REG_REG,
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OP_REG_REG3,
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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OP_IMM_REG_REG_REG,
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OP_PUSHPOP1,
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OP_PUSHPOP2,
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OP_PUSHPOP3,
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/* end-sanitize-v850eq */
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};
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#ifdef DEBUG
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void trace_input PARAMS ((char *name, enum op_types type, int size));
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void trace_output PARAMS ((enum op_types result));
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void trace_result PARAMS ((int has_result, unsigned32 result));
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extern int trace_num_values;
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extern unsigned32 trace_values[];
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extern unsigned32 trace_pc;
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extern const char *trace_name;
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extern const char *trace_module;
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#define TRACE_ALU_INPUT0() \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_module = "alu"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_num_values = 0; \
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} \
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} while (0)
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#define TRACE_ALU_INPUT1(IN1) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_module = "alu"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN1); \
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trace_num_values = 1; \
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} \
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} while (0)
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#define TRACE_ALU_INPUT2(IN1, IN2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_module = "alu"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN1); \
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trace_values[1] = (IN2); \
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trace_num_values = 2; \
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} \
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} while (0)
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#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_module = "alu"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN0); \
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trace_values[1] = (IN1); \
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trace_values[2] = (IN2); \
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trace_num_values = 3; \
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} \
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} while (0)
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#define TRACE_ALU_RESULT(RESULT) \
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do { \
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if (TRACE_ALU_P (CPU)) { \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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#define TRACE_BRANCH0() \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_module = "branch"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_num_values = 0; \
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trace_result (1, (nia)); \
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} \
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} while (0)
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#define TRACE_BRANCH1(IN1) \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_module = "branch"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN1); \
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trace_num_values = 1; \
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trace_result (1, (nia)); \
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} \
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} while (0)
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#define TRACE_BRANCH2(IN1, IN2) \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_module = "branch"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN1); \
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trace_values[1] = (IN2); \
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trace_num_values = 2; \
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trace_result (1, (nia)); \
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} \
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} while (0)
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#define TRACE_BRANCH3(IN1, IN2, IN3) \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_module = "branch"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (IN1); \
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trace_values[1] = (IN2); \
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trace_values[2] = (IN3); \
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trace_num_values = 3; \
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trace_result (1, (nia)); \
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} \
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} while (0)
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#define TRACE_LD(ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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/* start-sanitize-v850e */
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#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = (NAME); \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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/* end-sanitize-v850e */
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#define TRACE_ST(ADDR,RESULT) \
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do { \
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if (TRACE_MEMORY_P (CPU)) { \
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trace_module = "memory"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_values[0] = (ADDR); \
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trace_num_values = 1; \
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trace_result (1, (RESULT)); \
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} \
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} while (0)
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#else
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#define trace_input(NAME, IN1, IN2)
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#define trace_output(RESULT)
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#define trace_result(HAS_RESULT, RESULT)
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#define TRACE_ALU_INPUT0()
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#define TRACE_ALU_INPUT1(IN0)
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#define TRACE_ALU_INPUT2(IN0, IN1)
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#define TRACE_ALU_INPUT2(IN0, IN1)
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#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
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#define TRACE_ALU_RESULT(RESULT)
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#define TRACE_BRANCH0()
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#define TRACE_BRANCH1(IN1)
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#define TRACE_BRANCH2(IN1, IN2)
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#define TRACE_BRANCH2(IN1, IN2, IN3)
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#define TRACE_LD(ADDR,RESULT)
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#define TRACE_ST(ADDR,RESULT)
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#endif
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/* start-sanitize-v850eq */
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extern void divun ( unsigned int N,
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unsigned long int als,
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unsigned long int sfi,
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unsigned long int * quotient_ptr,
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unsigned long int * remainder_ptr,
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boolean * overflow_ptr
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);
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extern void divn ( unsigned int N,
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unsigned long int als,
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unsigned long int sfi,
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signed long int * quotient_ptr,
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signed long int * remainder_ptr,
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boolean * overflow_ptr
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);
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/* end-sanitize-v850eq */
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/* start-sanitize-v850e */
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extern int type1_regs[];
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extern int type2_regs[];
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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extern int type3_regs[];
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/* end-sanitize-v850eq */
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