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binutils-gdb/sim/common
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Dimitar Dimitrov ddd44b7053 sim: Add PRU simulator port 
A simulator port for the TI PRU I/O processor.

v1: https://sourceware.org/ml/gdb-patches/2016-12/msg00143.html
v2: https://sourceware.org/ml/gdb-patches/2017-02/msg00397.html
v3: https://sourceware.org/ml/gdb-patches/2017-02/msg00516.html
v4: https://sourceware.org/ml/gdb-patches/2018-06/msg00484.html
v5: https://sourceware.org/ml/gdb-patches/2019-08/msg00584.html
v6: https://sourceware.org/ml/gdb-patches/2019-09/msg00036.html

gdb/ChangeLog:

	* NEWS: Mention new simulator port for PRU.

sim/ChangeLog:

	* MAINTAINERS: Add myself as PRU maintainer.
	* configure: Regenerated.
	* configure.tgt: Add PRU.

sim/common/ChangeLog:

	* gennltvals.sh: Add PRU libgloss target.
	* nltvals.def: Regenerate from the latest libgloss sources.

sim/pru/ChangeLog:

	* Makefile.in: New file.
	* aclocal.m4: Regenerated.
	* config.in: Regenerated.
	* configure: Regenerated.
	* configure.ac: New file.
	* interp.c: New file.
	* pru.h: New file.
	* pru.isa: New file.
	* sim-main.h: New file.
2019-09-23 22:11:02 +01:00
..
acinclude.m4
aclocal.m4
callback.c
cgen-accfp.c sim/common: wire up new unordered comparisons 2019-06-13 21:27:10 +09:00
cgen-cpu.h
cgen-defs.h
cgen-engine.h
cgen-fpu.c
cgen-fpu.h sim/common: wire up new unordered comparisons 2019-06-13 21:27:10 +09:00
cgen-mem.h
cgen-ops.h sim: Use host not target byte order for merging and splitting values 2019-04-13 22:21:14 +01:00
cgen-par.c
cgen-par.h
cgen-run.c
cgen-scache.c
cgen-scache.h
cgen-sim.h
cgen-trace.c
cgen-trace.h
cgen-types.h
cgen-utils.c
cgen.sh
ChangeLog sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
configure
configure.ac
create-version.sh
dv-cfi.c
dv-cfi.h
dv-core.c
dv-glue.c
dv-pal.c
dv-sockser.c
dv-sockser.h
gdbinit.in
genmloop.sh
gennltvals.sh sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
gentmap.c
gentvals.sh
hw-alloc.c
hw-alloc.h
hw-base.c
hw-base.h
hw-device.c
hw-device.h
hw-events.c
hw-events.h
hw-handles.c
hw-handles.h
hw-instances.c
hw-instances.h
hw-main.h
hw-ports.c
hw-ports.h
hw-properties.c
hw-properties.h
hw-tree.c
hw-tree.h
Make-common.in
Makefile.in
nltvals.def sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
nrun.c
run.1
sim-abort.c
sim-alu.h
sim-arange.c
sim-arange.h
sim-assert.h
sim-base.h sim: fix all sim builds 2019-03-28 22:33:29 +00:00
sim-basics.h sim: fix all sim builds 2019-03-28 22:33:29 +00:00
sim-bits.c
sim-bits.h
sim-close.c
sim-command.c
sim-config.c
sim-config.h
sim-core.c
sim-core.h
sim-cpu.c
sim-cpu.h
sim-endian.c
sim-endian.h
sim-engine.c
sim-engine.h
sim-events.c
sim-events.h
sim-fpu.c
sim-fpu.h
sim-hload.c
sim-hrw.c
sim-hw.c
sim-hw.h
sim-info.c
sim-inline.c
sim-inline.h
sim-io.c
sim-io.h
sim-load.c bfd_section_* macros 2019-09-19 09:40:13 +09:30
sim-memopt.c
sim-memopt.h
sim-model.c
sim-model.h
sim-module.c
sim-module.h
sim-n-bits.h
sim-n-core.h
sim-n-endian.h
sim-options.c
sim-options.h
sim-profile.c
sim-profile.h
sim-reason.c
sim-reg.c
sim-resume.c
sim-run.c
sim-signal.c
sim-signal.h
sim-stop.c
sim-syscall.c
sim-syscall.h
sim-trace.c
sim-trace.h
sim-types.h
sim-utils.c bfd_section_* macros 2019-09-19 09:40:13 +09:30
sim-utils.h
sim-watch.c
sim-watch.h
syscall.c
version.h