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6f072a1034
This patch defines pseudo-registers "v0" through "v31" as aliases that map to the corresponding raw "vr0" through "vr31" vector registers for Power. The motivation behind this is that although GDB defines these registers as "vrX", the disassembler prints them as "vX", e.g. as the operands in instructions such as "vaddubm v2,v1,v1". This can be confusing to users trying to print out the values of the operands while inspecting the disassembled code. The new aliases are made not to belong to any register group, to avoid duplicated values in "info register vector" and "info register all". The arch-specific rs6000_pseudo_register_reggroup_p function had previously been removed since the other pseudo-registers could have their groups inferred by their type. It restored with this patch to handle the aliases. Membership for the other pseudo-registers is still determined using the default function. A new tests checks that GDB prints the expected values of vector registers after they are filled by the inferior, by using both the raw names and the aliases. Two other existing tests are modified to also test the aliases. gdb/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * ppc-tdep.h (struct gdbarch_tdep) <ppc_v0_alias_regnum>: New field. * rs6000-tdep.c: Include reggroups.h. (IS_V_ALIAS_PSEUDOREG): Define. (rs6000_register_name): Return names for the "vX" aliases. (rs6000_pseudo_register_type): Return type for the "vX" aliases. (rs6000_pseudo_register_reggroup_p): Restore. Handle "vX" aliases. Call default_register_reggroup_p for all other pseudo-registers. (v_alias_pseudo_register_read, v_alias_pseudo_register_write): New functions. (rs6000_pseudo_register_read, rs6000_pseudo_register_write): Handle "vX" aliases. (v_alias_pseudo_register_collect): New function. (rs6000_ax_pseudo_register_collect): Handle "vX" aliases. (rs6000_gdbarch_init): Initialize "vX" aliases as pseudo-registers. Restore registration of rs6000_pseudo_register_reggroup_p with set_tdesc_pseudo_register_reggroup_p. gdb/testsuite/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * gdb.arch/vsx-regs.exp: Add tests that use the vector register aliases. * gdb.arch/altivec-regs.exp: Likewise. Fix indentation of two tests. * gdb.arch/powerpc-vector-regs.c: New file. * gdb.arch/powerpc-vector-regs.exp: New file. gdb/doc/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * gdb.texinfo (PowerPC Features): Document the alias pseudo-registers for the org.gnu.gdb.power.altivec feature.
202 lines
9.1 KiB
Plaintext
202 lines
9.1 KiB
Plaintext
# Copyright (C) 2008-2019 Free Software Foundation, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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#
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# Test the use of VSX registers, for Powerpc.
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#
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if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
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verbose "Skipping vsx register tests."
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return
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}
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standard_testfile
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set compile_flags {debug nowarnings quiet}
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if [get_compiler_info] {
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warning "get_compiler failed"
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return -1
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}
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if [test_compiler_info gcc*] {
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set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
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} elseif [test_compiler_info xlc*] {
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set compile_flags "$compile_flags additional_flags=-qaltivec"
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} else {
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warning "unknown compiler"
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return -1
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}
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if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
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untested "failed to compile"
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return -1
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}
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gdb_start
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gdb_reinitialize_dir $srcdir/$subdir
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gdb_load ${binfile}
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# Run to `main' where we begin our tests.
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if ![runto_main] then {
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fail "can't run to main"
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return 0
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}
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set endianness [get_endianness]
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# Data sets used throughout the test
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if {$endianness == "big"} {
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set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
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set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
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set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
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set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
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set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
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set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
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} else {
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set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
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set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
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set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
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set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
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set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
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set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
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}
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set float_register ".raw 0xdeadbeefdeadbeef."
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# First run the F0~F31/VS0~VS31 tests
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# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test_no_output "set \$f$i = 1\.3"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
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}
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# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
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for {set i 0} {$i < 32} {incr i 1} {
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for {set j 0} {$j < 4} {incr j 1} {
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gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
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}
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
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}
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# Now run the VR0~VR31/VS32~VS63 tests
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# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
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for {set i 0} {$i < 32} {incr i 1} {
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for {set j 0} {$j < 4} {incr j 1} {
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gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
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}
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}
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for {set i 32} {$i < 64} {incr i 1} {
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gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
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}
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# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
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for {set i 32} {$i < 64} {incr i 1} {
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for {set j 0} {$j < 4} {incr j 1} {
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gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
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}
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
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gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i"
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}
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# Create a core file. We create the core file before the F32~F63/VR0~VR31 test
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# below because then we'll have more interesting register values to verify
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# later when loading the core file (i.e., different register values for different
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# vector register banks).
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set corefile [standard_output_file vsx-core.test]
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set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]
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# Now run the F32~F63/VR0~VR31 tests.
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# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
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for {set i 32} {$i < 64} {incr i 1} {
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gdb_test_no_output "set \$f$i = 1\.3"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
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gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)"
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}
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# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
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for {set i 0} {$i < 32} {incr i 1} {
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for {set j 0} {$j < 4} {incr j 1} {
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gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
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}
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}
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for {set i 32} {$i < 64} {incr i 1} {
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gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
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gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)"
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}
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# Test reading the core file.
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if {!$core_supported} {
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return -1
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}
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gdb_exit
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gdb_start
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gdb_reinitialize_dir $srcdir/$subdir
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gdb_load ${binfile}
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set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
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if { $core_loaded == -1 } {
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# No use proceeding from here.
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return
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}
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for {set i 0} {$i < 32} {incr i 1} {
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gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
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}
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for {set i 32} {$i < 64} {incr i 1} {
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gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"
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}
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