mirror of
https://sourceware.org/git/binutils-gdb.git
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322 lines
6.3 KiB
C
322 lines
6.3 KiB
C
# This shell script emits C code. -*- C -*-
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# Main loop and support routines for the M32R.
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# Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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# Contributed by Cygnus Support.
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#
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# This file is part of GDB, the GNU debugger.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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# Syntax:
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# /bin/sh mainloop.in {init|normal|fast|support}
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# ??? There's lots of conditional compilation here.
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# After a few more ports are done, revisit.
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case "x$1" in
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xinit)
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cat <<EOF
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#if defined (WITH_SCACHE) && defined (USE_SEM_SWITCH) && defined (__GNUC__)
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{
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static decode_init_p = 0;
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if (! decode_init_p)
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{
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/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "sem-switch.c"
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decode_init_p = 1;
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}
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}
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#endif
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EOF
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;;
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xnormal | xfast)
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cat <<EOF
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#if WITH_SCACHE
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{
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int hash;
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SCACHE *sc;
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/* First step: look up current insn in hash table. */
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hash = SCACHE_HASH_PC (sd, PC);
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sc = CPU_SCACHE_CACHE (current_cpu) + hash;
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/* If the entry isn't the one we want (cache miss),
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fetch and decode the instruction. */
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if (sc->argbuf.addr != PC)
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{
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PCADDR pc = PC;
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insn_t insn;
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#if ! FAST
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PROFILE_COUNT_SCACHE_MISS (current_cpu);
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#endif
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/* This only occurs when single stepping.
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The test is unnecessary otherwise, but the cost is teensy,
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compared with decoding/extraction. */
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if (pc & 3)
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{
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insn = GETMEMUHI (current_cpu, pc);
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do_extract_insn16 (current_cpu, pc, insn & 0x7fff, sc, FAST);
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}
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else
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{
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insn = GETMEMUSI (current_cpu, pc);
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if (insn & 0x80000000)
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{
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do_extract_insn32 (current_cpu, pc, insn, sc, FAST);
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}
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else
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{
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/* 2 16 bit insns. Ignore parallel case for now
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(2nd always nop). Decode both as we know there's room.
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??? Could do a test for an unconditional branch in the
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left slot if one wanted to. */
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do_extract_insn16 (current_cpu, pc, insn >> 16, sc, FAST);
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do_extract_insn16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST);
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}
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}
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}
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#if ! FAST
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else
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{
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PROFILE_COUNT_SCACHE_HIT (current_cpu);
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}
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#endif
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#if 0 /*FIXME:wip*/
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/* Run until we get a cache miss. */
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do
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{
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#if ! FAST
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TRACE_INSN_INIT (current_cpu);
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TRACE_INSN (current_cpu, sc->argbuf.opcode, &sc->argbuf, sc->argbuf.addr);
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#endif
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sc = (*sc->semantic.sem_fn) (current_cpu, sc);
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#if ! FAST
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TRACE_INSN_FINI (current_cpu);
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#endif
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}
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while (sc->argbuf.addr == PC);
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#if ! FAST
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PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
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#endif
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#else /* !wip */
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#if ! FAST
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TRACE_INSN_INIT (current_cpu);
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TRACE_INSN (current_cpu, sc->argbuf.opcode, &sc->argbuf, sc->argbuf.addr);
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#endif
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#if FAST && defined (USE_SEM_SWITCH)
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#define DEFINE_SWITCH
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#include "sem-switch.c"
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#else
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PC = (*sc->semantic.sem_fn) (current_cpu, sc);
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#endif
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#if ! FAST
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TRACE_INSN_FINI (current_cpu);
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PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
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#endif
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#endif /* !wip */
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}
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#else /* ! WITH_SCACHE */
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{
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insn_t insn;
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if (PC & 3)
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{
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insn = GETMEMUHI (current_cpu, PC);
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PC = do_insn16 (current_cpu, PC, insn & 0x7fff);
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}
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else
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{
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insn = GETMEMUSI (current_cpu, PC);
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if (insn & 0x80000000)
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{
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/* 32 bit insn */
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PC = do_insn32 (current_cpu, PC, insn);
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}
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else
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{
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/* 2 16 bit insns. Ignore parallel case for now
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(2nd always nop). */
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PCADDR oldpc = PC;
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PC = do_insn16 (current_cpu, PC, insn >> 16);
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if (PC == oldpc + 2)
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{
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PC = do_insn16 (current_cpu, PC, insn & 0x7fff);
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}
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}
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}
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}
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#endif /* ! WITH_SCACHE */
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EOF
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;;
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xsupport)
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cat <<EOF
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#if WITH_SCACHE
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#ifdef __GNUC__
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#define DO_INLINE inline
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#else
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#define DO_INLINE
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#endif
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/* FAST is optimized out by GCC. */
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static DO_INLINE void
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do_extract_insn16 (SIM_CPU *cpu, PCADDR pc, insn_t insn,
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SCACHE *sc, int fast)
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{
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DECODE *d = decode (insn);
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(*d->extract) (cpu, pc, insn, &sc->argbuf);
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if (fast)
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{
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#ifdef USE_SEM_SWITCH
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#ifdef __GNUC__
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sc->semantic.sem_case = d->semantic_lab;
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#else
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sc->semantic.sem_case = d->insn_type;
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#endif
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#else
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sc->semantic.sem_fn = d->semantic_fast;
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#endif
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}
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else
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{
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sc->semantic.sem_fn = d->semantic_fast;
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sc->argbuf.opcode = d->opcode;
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}
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sc->next = pc + 2;
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}
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static DO_INLINE void
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do_extract_insn32 (SIM_CPU *cpu, PCADDR pc, insn_t insn,
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SCACHE *sc, int fast)
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{
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/* 32 bit insn */
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DECODE *d = decode (insn >> 16);
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(*d->extract) (cpu, pc, insn, &sc->argbuf);
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if (fast)
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{
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#ifdef USE_SEM_SWITCH
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#ifdef __GNUC__
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sc->semantic.sem_case = d->semantic_lab;
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#else
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sc->semantic.sem_case = d->insn_type;
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#endif
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#else
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sc->semantic.sem_fn = d->semantic_fast;
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#endif
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}
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else
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{
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sc->semantic.sem_fn = d->semantic_fast;
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sc->argbuf.opcode = d->opcode;
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}
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sc->next = pc + 4;
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}
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#endif /* WITH_SCACHE */
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static PCADDR
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do_insn16 (cpu, pc, insn)
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SIM_CPU *cpu;
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PCADDR pc;
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insn_t insn;
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{
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DECODE *d;
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ARGBUF argbuf;
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d = decode (insn);
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(*d->extract) (cpu, pc, insn, &argbuf);
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argbuf.opcode = d->opcode;
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TRACE_INSN_INIT (cpu);
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TRACE_INSN (cpu, d->opcode, &argbuf, pc);
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pc = (*d->semantic) (cpu, &argbuf);
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TRACE_INSN_FINI (cpu);
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PROFILE_COUNT_INSN (cpu, pc, d->insn_type);
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return pc;
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}
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static PCADDR
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do_insn32 (cpu, pc, insn)
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SIM_CPU *cpu;
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PCADDR pc;
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insn_t insn;
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{
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DECODE *d;
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ARGBUF argbuf;
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d = decode (insn >> 16);
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(*d->extract) (cpu, pc, insn, &argbuf);
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argbuf.opcode = d->opcode;
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TRACE_INSN_INIT (cpu);
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TRACE_INSN (cpu, d->opcode, &argbuf, pc);
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pc = (*d->semantic) (cpu, &argbuf);
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TRACE_INSN_FINI (cpu);
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PROFILE_COUNT_INSN (cpu, pc, d->insn_type);
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return pc;
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}
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EOF
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;;
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*)
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echo "Invalid argument to mainloop.in: $1" >&2
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exit 1
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;;
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esac
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