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binutils-gdb/sim
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Nelson Chu 5a9f5403c7 RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,

[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM:            Renamed from SBTYPE_IMM.
JTYPE_IMM:            Renamed from UJTYPE_IMM.
CITYPE_IMM:           Renamed from RVC_IMM.
CITYPE_LUI_IMM:       Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM:  Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM:      Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM:      Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM:          Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM:          Added for .insn without special encoding.
CSSTYPE_SWSP_IMM:     Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM:     Renamed from RVC_SDSP_IMM.
CLTYPE_IMM:           Added for .insn without special encoding.
CLTYPE_LW_IMM:        Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM:        Renamed from RVC_LD_IMM.
RVC_SIMM3:            Unused and removed.
CBTYPE_IMM:           Renamed from RVC_B_IMM.
CJTYPE_IMM:           Renamed from RVC_J_IMM.

* Added new operands and removed the unused ones,

C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.

bfd/
    PR 27158
    * elfnn-riscv.c (perform_relocation): Updated encoding macros.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    * elfxx-riscv.c (howto_table): Likewise.
gas/
    PR 27158
    * config/tc-riscv.c (riscv_ip): Updated encoding macros.
    (md_apply_fix): Likewise.
    (md_convert_frag_branch): Likewise.
    (validate_riscv_insn): Likewise.  Also arranged operands, including
    added C5 and C6 operands, and removed unused Ci and C< operands.
    * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
    * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
    * testsuite/gas/riscv/insn.s: Likewise.
gdb/
    PR 27158
    * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
    (decode_j_type_insn): Likewise.
    (decode_cj_type_insn): Likewise.
    (decode_b_type_insn): Likewise.
    (decode): Likewise.
include/
    PR 27158
    * opcode/riscv.h: Updated encoding macros.
opcodes/
    PR 27158
    * riscv-dis.c (print_insn_args): Updated encoding macros.
    * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
    (match_c_addi16sp): Updated encoding macros.
    (match_c_lui): Likewise.
    (match_c_lui_with_hint): Likewise.
    (match_c_addi4spn): Likewise.
    (match_c_slli): Likewise.
    (match_slli_as_c_slli): Likewise.
    (match_c_slli64): Likewise.
    (match_srxi_as_c_srxi): Likewise.
    (riscv_insn_types): Added .insn css/cl/cs.
sim/
    PR 27158
    * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-19 11:44:49 +08:00
..
aarch64 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
arm sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
avr sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
bfin sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
bpf sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
common sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
cr16 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
cris sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
d10v sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
erc32 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
frv sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
ft32 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
h8300 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
igen sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
iq2000 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
lm32 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
m32c sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
m32r sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
m68hc11 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
mcore sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
microblaze sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
mips sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
mn10300 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
moxie sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
msp430 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
or1k sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
ppc sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
pru sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
riscv RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 2021-02-19 11:44:49 +08:00
rl78 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
rx sim: rx: mitigate fread warning 2021-02-13 02:44:36 -05:00
sh sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
testsuite sim: testsuite: push $arch out to targets 2021-02-13 12:14:25 -05:00
v850 sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
.gitignore
ChangeLog RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 2021-02-19 11:44:49 +08:00
configure sim: testsuite: push $arch out to targets 2021-02-13 12:14:25 -05:00
configure.ac sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00
configure.tgt sim: testsuite: push $arch out to targets 2021-02-13 12:14:25 -05:00
MAINTAINERS
Makefile.in sim: common: change gennltvals helper to Python 2021-01-30 20:17:46 -05:00
README-HACKING sim: switch to AC_CONFIG_MACRO_DIRS 2021-02-13 00:24:20 -05:00