mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
c213164ad2
This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
55 lines
2.2 KiB
Makefile
55 lines
2.2 KiB
Makefile
#source: tlsie.s
|
|
#as: -a64 -mfuture
|
|
#ld: -melf64ppc
|
|
#objdump: -dr -Mfuture
|
|
|
|
.*: file format .*
|
|
|
|
Disassembly of section \.text:
|
|
|
|
.*:
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (39 4d 90 08|08 90 4d 39) addi r10,r13,-28664
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 90 10|10 90 6d 38) addi r3,r13,-28656
|
|
.*: (06 03 ff ff|ff ff 03 06) paddi r4,r13,-28648
|
|
.*: (38 8d 90 18|18 90 8d 38)
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (39 4d 90 20|20 90 4d 39) addi r10,r13,-28640
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (60 00 00 00|00 00 00 60) nop
|
|
.*: (38 6d 90 20|20 90 6d 38) addi r3,r13,-28640
|
|
.*: (06 03 ff ff|ff ff 03 06) paddi r30,r13,-28640
|
|
.*: (3b cd 90 20|20 90 cd 3b)
|
|
.*: (7f c3 f3 78|78 f3 c3 7f) mr r3,r30
|
|
.*: (80 9e 00 00|00 00 9e 80) lwz r4,0\(r30\)
|
|
.*: (84 9e 00 00|00 00 9e 84) lwzu r4,0\(r30\)
|
|
.*: (88 be 00 00|00 00 be 88) lbz r5,0\(r30\)
|
|
.*: (8c be 00 00|00 00 be 8c) lbzu r5,0\(r30\)
|
|
.*: (90 de 00 00|00 00 de 90) stw r6,0\(r30\)
|
|
.*: (94 de 00 00|00 00 de 94) stwu r6,0\(r30\)
|
|
.*: (98 fe 00 00|00 00 fe 98) stb r7,0\(r30\)
|
|
.*: (9c fe 00 00|00 00 fe 9c) stbu r7,0\(r30\)
|
|
.*: (a1 1e 00 00|00 00 1e a1) lhz r8,0\(r30\)
|
|
.*: (a5 1e 00 00|00 00 1e a5) lhzu r8,0\(r30\)
|
|
.*: (a9 3e 00 00|00 00 3e a9) lha r9,0\(r30\)
|
|
.*: (ad 3e 00 00|00 00 3e ad) lhau r9,0\(r30\)
|
|
.*: (b1 5e 00 00|00 00 5e b1) sth r10,0\(r30\)
|
|
.*: (b5 5e 00 00|00 00 5e b5) sthu r10,0\(r30\)
|
|
.*: (c1 7e 00 00|00 00 7e c1) lfs f11,0\(r30\)
|
|
.*: (c5 7e 00 00|00 00 7e c5) lfsu f11,0\(r30\)
|
|
.*: (c9 9e 00 00|00 00 9e c9) lfd f12,0\(r30\)
|
|
.*: (cd 9e 00 00|00 00 9e cd) lfdu f12,0\(r30\)
|
|
.*: (d1 be 00 00|00 00 be d1) stfs f13,0\(r30\)
|
|
.*: (d5 be 00 00|00 00 be d5) stfsu f13,0\(r30\)
|
|
.*: (d9 de 00 00|00 00 de d9) stfd f14,0\(r30\)
|
|
.*: (dd de 00 00|00 00 de dd) stfdu f14,0\(r30\)
|
|
.*: (e9 fe 00 00|00 00 fe e9) ld r15,0\(r30\)
|
|
.*: (e9 fe 00 01|01 00 fe e9) ldu r15,0\(r30\)
|
|
.*: (fa 1e 00 00|00 00 1e fa) std r16,0\(r30\)
|
|
.*: (fa 1e 00 01|01 00 1e fa) stdu r16,0\(r30\)
|
|
.*: (ea 3e 00 02|02 00 3e ea) lwa r17,0\(r30\)
|