binutils-gdb/ld/testsuite/ld-powerpc/tlsopt5.wf
Alan Modra 3cd7c7d7ef PPC64_OPT_LOCALENTRY is incompatible with tail calls
The save of r2 in __glink_PLTresolve is the culprit.  Remove it,
unless we know we need it for --plt-localentry.  --plt-localentry
should not be used with power10 pc-relative code that makes tail
calls.

The patch also removes use of r2 as a scratch reg in the ELFv2
__glink_PLTresolve.  Using r2 isn't a problem, this is just reducing
the number of scratch regs.

bfd/
	* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Depend on has_plt_localentry0.
	(LD_R0_0R11, ADD_R11_R0_R11): Define.
	(ppc64_elf_tls_setup): Disable params->plt_localentry0 when power10
	code detected.
	(ppc64_elf_size_stubs): Update __glink_PLTresolve eh_frame.
	(ppc64_elf_build_stubs): Move r2 save to start of __glink_PLTresolve,
	and only emit for has_plt_localentry0.  Don't use r2 in the stub.
ld/
	* testsuite/ld-powerpc/elfv2so.d,
	* testsuite/ld-powerpc/notoc2.d,
	* testsuite/ld-powerpc/tlsdesc.wf,
	* testsuite/ld-powerpc/tlsdesc2.d,
	* testsuite/ld-powerpc/tlsdesc2.wf,
	* testsuite/ld-powerpc/tlsopt5.d,
	* testsuite/ld-powerpc/tlsopt5.wf,
	* testsuite/ld-powerpc/tlsopt6.d,
	* testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.
2020-09-26 19:03:02 +09:30

28 lines
641 B
Plaintext

Contents of the \.eh_frame section:
0+ 0+10 0+ CIE
Version: 1
Augmentation: "zR"
Code alignment factor: 4
Data alignment factor: -8
Return address column: 65
Augmentation data: 1b
DW_CFA_def_cfa: r1 ofs 0
0+14 0+14 0+18 FDE cie=0+ pc=.*
DW_CFA_advance_loc: 80 to .*
DW_CFA_offset_extended_sf: r65 at cfa\+8
DW_CFA_advance_loc: 16 to .*
DW_CFA_restore_extended: r65
0+2c 0+14 0+30 FDE cie=0+ pc=.*
DW_CFA_advance_loc: 8 to .*
DW_CFA_register: r65 in r0
DW_CFA_advance_loc: 8 to .*
DW_CFA_restore_extended: r65
0+44 0+10 0+48 FDE cie=0+ pc=.*
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop