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313 lines
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Plaintext
313 lines
10 KiB
Plaintext
@c Copyright 1996, 1997, 1998, 1999, 2000, 2001
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node ARM-Dependent
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@chapter ARM Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter ARM Dependent Features
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@end ifclear
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@cindex ARM support
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@cindex Thumb support
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@menu
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* ARM Options:: Options
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* ARM Syntax:: Syntax
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* ARM Floating Point:: Floating Point
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* ARM Directives:: ARM Machine Directives
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* ARM Opcodes:: Opcodes
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@end menu
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@node ARM Options
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@section Options
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@cindex ARM options (none)
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@cindex options for ARM (none)
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@table @code
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@cindex @code{-marm} command line option, ARM
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@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
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@itemx -mxscale
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@itemx -marm9e
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This option specifies the target processor. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor.
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The option @code{-marm9e} specifies that the target processor is the
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Cirrus ARM processor with the Maverick DSP co-processor.
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@cindex @code{-marmv} command line option, ARM
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@item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
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This option specifies the target architecture. The assembler will issue
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an error message if an attempt is made to assemble an instruction which
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will not execute on the target architecture.
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The option @code{-marmv5te} specifies that v5t architecture should be
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used with the El Segundo extensions enabled.
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@cindex @code{-mthumb} command line option, ARM
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@item -mthumb
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This option specifies that only Thumb instructions should be assembled.
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@cindex @code{-mall} command line option, ARM
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@item -mall
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This option specifies that any Arm or Thumb instruction should be assembled.
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@cindex @code{-mfpa} command line option, ARM
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@item -mfpa @code{[10|11]}
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This option specifies the floating point architecture in use on the
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target processor.
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@cindex @code{-mfpe-old} command line option, ARM
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@item -mfpe-old
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Do not allow the assembly of floating point multiple instructions.
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@cindex @code{-mno-fpu} command line option, ARM
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@item -mno-fpu
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Do not allow the assembly of any floating point instructions.
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@cindex @code{-mthumb-interwork} command line option, ARM
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@item -mthumb-interwork
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This option specifies that the output generated by the assembler should
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be marked as supporting interworking.
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@cindex @code{-mapcs} command line option, ARM
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@item -mapcs @code{[26|32]}
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This option specifies that the output generated by the assembler should
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be marked as supporting the indicated version of the Arm Procedure.
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Calling Standard.
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@cindex @code{-matpcs} command line option, ARM
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@item -matpcs
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This option specifies that the output generated by the assembler should
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be marked as supporting the Arm/Thumb Procedure Calling Standard. If
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enabled this option will cause the assembler to create an empty
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debugging section in the object file called .arm.atpcs. Debuggers can
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use this to determine the ABI being used by.
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@cindex @code{-mapcs-float} command line option, ARM
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@item -mapcs-float
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This indicates the the floating point variant of the APCS should be
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used. In this variant floating point arguments are passed in FP
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registers rather than integer registers.
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@cindex @code{-mapcs-reentrant} command line option, ARM
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@item -mapcs-reentrant
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This indicates that the reentrant variant of the APCS should be used.
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This variant supports position independent code.
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@cindex @code{-EB} command line option, ARM
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command line option, ARM
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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@cindex @code{-k} command line option, ARM
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@cindex PIC code generation for ARM
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@item -k
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This option specifies that the output of the assembler should be marked
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as position-independent code (PIC).
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@cindex @code{-moabi} command line option, ARM
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@item -moabi
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This indicates that the code should be assembled using the old ARM ELF
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conventions, based on a beta release release of the ARM-ELF
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specifications, rather than the default conventions which are based on
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the final release of the ARM-ELF specifications.
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@end table
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@node ARM Syntax
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@section Syntax
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@menu
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* ARM-Chars:: Special Characters
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* ARM-Regs:: Register Names
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@end menu
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@node ARM-Chars
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@subsection Special Characters
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@cindex line comment character, ARM
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@cindex ARM line comment character
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The presence of a @samp{@@} on a line indicates the start of a comment
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that extends to the end of the current line. If a @samp{#} appears as
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the first character of a line, the whole line is treated as a comment.
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@cindex line separator, ARM
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@cindex statement separator, ARM
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@cindex ARM line separator
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The @samp{;} character can be used instead of a newline to separate
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statements.
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@cindex immediate character, ARM
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@cindex ARM immediate character
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Either @samp{#} or @samp{$} can be used to indicate immediate operands.
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@cindex identifiers, ARM
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@cindex ARM identifiers
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*TODO* Explain about /data modifier on symbols.
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@node ARM-Regs
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@subsection Register Names
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@cindex ARM register names
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@cindex register names, ARM
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*TODO* Explain about ARM register naming, and the predefined names.
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@node ARM Floating Point
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@section Floating Point
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@cindex floating point, ARM (@sc{ieee})
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@cindex ARM floating point (@sc{ieee})
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The ARM family uses @sc{ieee} floating-point numbers.
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@node ARM Directives
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@section ARM Machine Directives
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@cindex machine directives, ARM
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@cindex ARM machine directives
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@table @code
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@cindex @code{align} directive, ARM
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@item .align @var{expression} [, @var{expression}]
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This is the generic @var{.align} directive. For the ARM however if the
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first argument is zero (ie no alignment is needed) the assembler will
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behave as if the argument had been 2 (ie pad to the next four byte
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boundary). This is for compatability with ARM's own assembler.
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@cindex @code{req} directive, ARM
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@item @var{name} .req @var{register name}
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This creates an alias for @var{register name} called @var{name}. For
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example:
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@smallexample
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foo .req r0
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@end smallexample
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@cindex @code{code} directive, ARM
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@item .code @code{[16|32]}
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This directive selects the instruction set being generated. The value 16
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selects Thumb, with the value 32 selecting ARM.
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@cindex @code{thumb} directive, ARM
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@item .thumb
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This performs the same action as @var{.code 16}.
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@cindex @code{arm} directive, ARM
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@item .arm
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This performs the same action as @var{.code 32}.
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@cindex @code{force_thumb} directive, ARM
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@item .force_thumb
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This directive forces the selection of Thumb instructions, even if the
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target processor does not support those instructions
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@cindex @code{thumb_func} directive, ARM
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@item .thumb_func
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This directive specifies that the following symbol is the name of a
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Thumb encoded function. This information is necessary in order to allow
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the assembler and linker to generate correct code for interworking
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between Arm and Thumb instructions and should be used even if
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interworking is not going to be performed. The presence of this
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directive also implies @code{.thumb}
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@cindex @code{thumb_set} directive, ARM
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@item .thumb_set
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This performs the equivalent of a @code{.set} directive in that it
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creates a symbol which is an alias for another symbol (possibly not yet
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defined). This directive also has the added property in that it marks
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the aliased symbol as being a thumb function entry point, in the same
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way that the @code{.thumb_func} directive does.
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@cindex @code{.ltorg} directive, ARM
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@item .ltorg
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This directive causes the current contents of the literal pool to be
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dumped into the current section (which is assumed to be the .text
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section) at the current location (aligned to a word boundary).
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@cindex @code{.pool} directive, ARM
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@item .pool
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This is a synonym for .ltorg.
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@end table
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@node ARM Opcodes
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@section Opcodes
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@cindex ARM opcodes
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@cindex opcodes for ARM
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@code{@value{AS}} implements all the standard ARM opcodes. It also
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implements several pseudo opcodes, including several synthetic load
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instructions.
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@table @code
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@cindex @code{NOP} pseudo op, ARM
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@item NOP
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@smallexample
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nop
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@end smallexample
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This pseudo op will always evaluate to a legal ARM instruction that does
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nothing. Currently it will evaluate to MOV r0, r0.
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@cindex @code{LDR reg,=<label>} pseudo op, ARM
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@item LDR
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@smallexample
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ldr <register> , = <expression>
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@end smallexample
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If expression evaluates to a numeric constant then a MOV or MVN
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instruction will be used in place of the LDR instruction, if the
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constant can be generated by either of these instructions. Otherwise
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the constant will be placed into the nearest literal pool (if it not
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already there) and a PC relative LDR instruction will be generated.
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@cindex @code{ADR reg,<label>} pseudo op, ARM
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@item ADR
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@smallexample
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adr <register> <label>
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@end smallexample
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This instruction will load the address of @var{label} into the indicated
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register. The instruction will evaluate to a PC relative ADD or SUB
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instruction depending upon where the label is located. If the label is
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out of range, or if it is not defined in the same file (and section) as
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the ADR instruction, then an error will be generated. This instruction
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will not make use of the literal pool.
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@cindex @code{ADRL reg,<label>} pseudo op, ARM
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@item ADRL
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@smallexample
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adrl <register> <label>
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@end smallexample
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This instruction will load the address of @var{label} into the indicated
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register. The instruction will evaluate to one or two PC relative ADD
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or SUB instructions depending upon where the label is located. If a
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second instruction is not needed a NOP instruction will be generated in
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its place, so that this instruction is always 8 bytes long.
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If the label is out of range, or if it is not defined in the same file
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(and section) as the ADRL instruction, then an error will be generated.
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This instruction will not make use of the literal pool.
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@end table
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For information on the ARM or Thumb instruction sets, see @cite{ARM
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Software Development Toolkit Reference Manual}, Advanced RISC Machines
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Ltd.
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